Datasheet > 74ALVC162334ADGG:5

74ALVC162334ADGG:5

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74ALVC162334ADGG:5 数据手册

74ALVC162334A

16-bit registered driver with inverted register enable and 30 Ω

termination resistors (3-state)

Rev. 03 — 13 December 2006

Product data sheet

1. General description

The 74ALVC162334A is a 16-bit universal bus driver. Data ﬂow is controlled by

active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP).

When LE is LOW, the A to Y data ﬂow is transparent. When LE is HIGH and CP is held at

LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is

stored in the latch/ﬂip-ﬂop.

The 74ALVC162334A is designed with 30 Ω series resistors in both HIGH or LOW output

stages.

When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the

high-impedance OFF-state. Operation of the OE input does not affect the state of the

latch/ﬂip-ﬂop.

To ensure the high-impedance state during power-up or power-down, OE should be tied to

V_CCthrough a pull-up resistor; the minimum value of the resistor is determined by the

current-sinking capability of the driver.

2. Features

I Wide supply voltage range of 1.2 V to 3.6 V

I Complies with JEDEC standard 8-1A

I CMOS low power consumption

I Direct interface with TTL levels

I Current drive: ±24 mA at 3.0 V

I MULTIBYTE ﬂow-through standard pinout architecture

I Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

I Output drive capability 50 Ω transmission lines at 85 °C

I Integrated 30 Ω termination resistors

I Input diodes to accommodate strong drivers

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