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74ALVC162373TX PDF预览

74ALVC162373TX

更新时间： 2024-11-21 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
6页 98K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48

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74ALVC162373TX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153, TSSOP-48
针数：48Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.53
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：12.5 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：2
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：9.8 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

74ALVC162373TX 数据手册

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November 2001  
Revised November 2001  
74ALVC162373  
Low Voltage 16-Bit Transparent Latch  
with 3.6V Tolerant Inputs and Outputs  
and 26Ω Series Resistors in Outputs  
General Description  
Features  
■ 1.65V to 3.6V VCC supply operation  
The ALVC162373 contains sixteen non-inverting latches  
with 3-STATE outputs and is intended for bus oriented  
applications. The device is byte controlled. The flip-flops  
appear to be transparent to the data when the Latch enable  
(LE) is HIGH. When LE is LOW, the data that meets the  
setup time is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the out-  
puts are in a high impedance state.  
■ 3.6V tolerant inputs and outputs  
■ 26Ω series resistors in outputs  
■ tPD (In to On)  
3.8 ns max for 3.0V to 3.6V VCC  
5.0 ns max for 2.3V to 2.7V VCC  
9.0 ns max for 1.65V to 1.95V VCC  
The ALVC162373 is also designed with 26Ω resistors in  
the outputs. This design reduces line noise in applications  
such as memory address drivers, clock drivers and bus  
transceivers/transmitters.  
■ Power-off high impedance inputs and outputs  
■ Support live insertion and withdrawal (Note 1)  
■ Uses patented noise/EMI reduction circuitry  
■ Latchup conforms to JEDEC JED78  
■ ESD performance:  
The 74ALVC162373 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
The 74ALVC162373 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Ordering Number Package Number  
Package Description  
74ALVC162373T  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
LEn  
Output Enable Input (Active LOW)  
Latch Enable Input  
Inputs  
I0–I15  
O0–O15  
Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS500709  
www.fairchildsemi.com  
123456

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