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74ALVC162373 PDF预览

74ALVC162373

更新时间: 2024-10-01 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
6页 98K
描述
Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in Outputs

74ALVC162373 数据手册

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November 2001  
Revised November 2001  
74ALVC162373  
Low Voltage 16-Bit Transparent Latch  
with 3.6V Tolerant Inputs and Outputs  
and 26Series Resistors in Outputs  
General Description  
Features  
1.65V to 3.6V VCC supply operation  
The ALVC162373 contains sixteen non-inverting latches  
with 3-STATE outputs and is intended for bus oriented  
applications. The device is byte controlled. The flip-flops  
appear to be transparent to the data when the Latch enable  
(LE) is HIGH. When LE is LOW, the data that meets the  
setup time is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the out-  
puts are in a high impedance state.  
3.6V tolerant inputs and outputs  
26series resistors in outputs  
tPD (In to On)  
3.8 ns max for 3.0V to 3.6V VCC  
5.0 ns max for 2.3V to 2.7V VCC  
9.0 ns max for 1.65V to 1.95V VCC  
The ALVC162373 is also designed with 26resistors in  
the outputs. This design reduces line noise in applications  
such as memory address drivers, clock drivers and bus  
transceivers/transmitters.  
Power-off high impedance inputs and outputs  
Support live insertion and withdrawal (Note 1)  
Uses patented noise/EMI reduction circuitry  
Latchup conforms to JEDEC JED78  
ESD performance:  
The 74ALVC162373 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
The 74ALVC162373 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Ordering Number Package Number  
Package Description  
74ALVC162373T  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
LEn  
Output Enable Input (Active LOW)  
Latch Enable Input  
Inputs  
I0I15  
O0O15  
Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS500709  
www.fairchildsemi.com  

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