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74AHCT164BQ,115 PDF预览

74AHCT164BQ,115

更新时间: 2024-11-18 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路触发器
页数 文件大小 规格书
18页 92K
描述
74AHC(T)164 - 8-bit serial-in/parallel-out shift register QFN 14-Pin

74AHCT164BQ,115 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SAT-762-1, DHVQFN-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:8.27
计数方向:RIGHT系列:AHCT/VHCT/VT
JESD-30 代码:R-PQCC-N14JESD-609代码:e4
长度:3 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:65000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC14,.1X.12,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:Shift Registers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
最小 fmax:85 MHzBase Number Matches:1

74AHCT164BQ,115 数据手册

 浏览型号74AHCT164BQ,115的Datasheet PDF文件第2页浏览型号74AHCT164BQ,115的Datasheet PDF文件第3页浏览型号74AHCT164BQ,115的Datasheet PDF文件第4页浏览型号74AHCT164BQ,115的Datasheet PDF文件第5页浏览型号74AHCT164BQ,115的Datasheet PDF文件第6页浏览型号74AHCT164BQ,115的Datasheet PDF文件第7页 
74AHC164; 74AHCT164  
8-bit serial-in/parallel-out shift register  
Rev. 03 — 24 April 2008  
Product data sheet  
1. General description  
The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is  
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with  
JEDEC standard No. 7A.  
The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA  
or DSB); either input can be used as an active HIGH enable for data entry through the  
other input. Both inputs must be connected together or an unused input must be tied  
HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)  
and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)  
that existed one set-up time prior to the rising clock edge.  
A LOW-level on the master reset (MR) input overrides all other inputs and clears the  
register asynchronously, forcing all outputs LOW.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC164: CMOS level  
N For 74AHCT164: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

74AHCT164BQ,115 替代型号

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74AHCT164D,118 NXP

完全替代

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