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74ACTQ646SPC PDF预览

74ACTQ646SPC

更新时间: 2024-10-31 23:24:03
品牌 Logo 应用领域
其他 - ETC 总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 99K
描述
Single 8-bit Bus Transceiver

74ACTQ646SPC 数据手册

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January 1990  
Revised September 2000  
74ACQ646 74ACTQ646  
Quiet Series Octal Transceiver/Register  
with 3-STATE Outputs  
General Description  
Features  
Guaranteed simultaneous switching noise level and  
The ACQ/ACTQ646 consist of registered bus transceiver  
circuits, with outputs, D-type flip-flops, and control circuitry  
providing multiplexed transmission of data directly from the  
input bus or from the internal storage registers. Data on the  
A or B bus will be loaded into the respective registers on  
the LOW-to-HIGH transition of the appropriate clock pin  
(CPAB or CPBA). The four fundamental handling functions  
available are illustrated in Figure 1, Figure 2, Figure 3 and  
Figure 4.  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Independent registers for A and B busses  
Multiplexed real-time and stored data transfers  
300 mil slim dual-in-line package  
Outputs source/sink 24 mA  
Faster prop delays than the standard AC/ACT646  
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-  
ogy to guarantee quiet output switching and improved  
dynamic threshold performance. FACT Quiet Series fea-  
tures GTO output control and undershoot corrector in  
addition to a split ground bus for superior performance.  
Ordering Code:  
Order Number  
74ACQ646SC  
Package Number  
M24B  
Package Description  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
74ACQ464ASPC  
74ACTQ646SC  
74ACTQ464ASPC  
N24C  
M24B  
N24C  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
A0A7  
Descriptions  
Data Register A Inputs  
Data Register A Outputs  
Data Register B Inputs  
Data Register B Outputs  
Clock Pulse Inputs  
B0B7  
CPAB, CPBA  
SAB, SBA  
G
Transmit/Receive Inputs  
Output Enable Input  
DIR  
Direction Control Input  
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation  
© 2000 Fairchild Semiconductor Corporation  
DS010635  
www.fairchildsemi.com  

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