74ACT377

更新时间： 2024-11-13 22:56:15

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器时钟
页数	文件大小	规格书
9页	103K
描述
Octal D-Type Flip-Flop with Clock Enable

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数据手册

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74ACT377 数据手册

November 1988

Revised November 1999

74AC377 • 74ACT377

Octal D-Type Flip-Flop with Clock Enable

General Description

Features

The AC/ACT377 has eight edge-triggered, D-type flip-flops

with individual D inputs and Q outputs. The common buff-

ered Clock (CP) input loads all flip-flops simultaneously,

when the Clock Enable (CE) is LOW.

■ I_CCreduced by 50%

■ Ideal for addressable register applications

■ Clock enable for address and data synchronization

applications

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

The CE input must be stable only one setup time prior to

the LOW-to-HIGH clock transition for predictable operation.

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

■ Outputs source/sink 24 mA

■ See 273 for master reset version

■ See 373 for transparent latch version

■ See 374 for 3-STATE version

■ ACT377 has TTL-compatible inputs

Ordering Code:

Order Number Package Number

Package Description

74AC377SC

74AC377SJ

M20B

M20D

MTC20

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC377MTC

74AC377PC

74ACT377SC

74ACT377SJ

74ACT377MTC

74ACT377PC

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

M20B

M20D

MTC20

N20A

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

D₀–D₇

Description

Data Inputs

Clock Enable (Active LOW)

Data Outputs

Q₀–Q₇

Clock Pulse Input

FACT is a trademark of Fairchild Semiconductor Corporation.

DS009961

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与74ACT377相关器件

型号	品牌	获取价格	描述	数据表
74ACT377FC	TI	获取价格	ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20
74ACT377FCQR	TI	获取价格	ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20, CERAMIC, FP-20
74ACT377FCXR	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20
74ACT377LC	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20
74ACT377LCT	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20
74ACT377LCTR	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20
74ACT377LCX	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20
74ACT377LCXR	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20
74ACT377MTC	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74ACT377MTCX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable

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