74ACT377PCX

更新时间： 2024-11-14 00:01:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器时钟
页数	文件大小	规格书
10页	120K
描述
Octal D-Type Flip-Flop with Clock Enable

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74ACT377PCX 数据手册

November 1988

Revised March 2005

74AC377 • 74ACT377

Octal D-Type Flip-Flop with Clock Enable

General Description

Features

The AC/ACT377 has eight edge-triggered, D-type flip-flops

with individual D inputs and Q outputs. The common buff-

ered Clock (CP) input loads all flip-flops simultaneously,

when the Clock Enable (CE) is LOW.

■ I_CCreduced by 50%

■ Ideal for addressable register applications

■ Clock enable for address and data synchronization

applications

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

The CE input must be stable only one setup time prior to

the LOW-to-HIGH clock transition for predictable operation.

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

■ Outputs source/sink 24 mA

■ See 273 for master reset version

■ See 373 for transparent latch version

■ See 374 for 3-STATE version

■ ACT377 has TTL-compatible inputs

Ordering Code:

Package

Order Number

Package Description

Number

74AC377SC

74AC377SJ

74AC377MTC

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MTC20

74AC377MTCX_NL

(Note 1)

Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74AC377PC

N20A

M20B

M20D

MTC20

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT377SC

74ACT377SJ

74ACT377MTC

74ACT377PC

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Connection Diagram

Pin Descriptions

Pin Names

Description

D₀–D₇

Data Inputs

Clock Enable (Active LOW)

Data Outputs

Q₀–Q₇

Clock Pulse Input

FACT is a trademark of Fairchild Semiconductor Corporation.

DS009961

www.fairchildsemi.com

12 3 4 5 6 7...10

中文翻译

下载PDF

与74ACT377PCX相关器件

型号	品牌	获取价格	描述	数据表
74ACT377SC	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74ACT377SC	ROCHESTER	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT377SCQR	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT377SCT	FAIRCHILD	获取价格	暂无描述
74ACT377SCX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74ACT377SCX	ROCHESTER	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT377SCX_NL	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT377SCXR	FAIRCHILD	获取价格	D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
74ACT377SJ	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74ACT377SJ	TI	获取价格	ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20

与74ACT377PCX相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

5
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

2
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

29
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

12

产品中心

服务支持

精选活动

关于我们

帮助中心

74ACT377PCX

74ACT377PCX 数据手册

与74ACT377PCX相关器件

与74ACT377PCX相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74ACT377PCX

74ACT377PCX 数据手册

与74ACT377PCX相关器件

与74ACT377PCX相关文章

您还可以找

您在本页遇到什么问题？