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74ACT11873N PDF预览

74ACT11873N

更新时间: 2024-11-21 13:04:55
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
7页 114K
描述
IC,LATCH,DUAL,4-BIT,ACT-CMOS,DIP,28PIN,PLASTIC

74ACT11873N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:NJESD-30 代码:R-PDIP-T28
逻辑集成电路类型:D LATCH位数:4
功能数量:2端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.6
封装形状:RECTANGULAR封装形式:IN-LINE
电源:3.3/5 V认证状态:Not Qualified
子类别:FF/Latches表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

74ACT11873N 数据手册

 浏览型号74ACT11873N的Datasheet PDF文件第2页浏览型号74ACT11873N的Datasheet PDF文件第3页浏览型号74ACT11873N的Datasheet PDF文件第4页浏览型号74ACT11873N的Datasheet PDF文件第5页浏览型号74ACT11873N的Datasheet PDF文件第6页浏览型号74ACT11873N的Datasheet PDF文件第7页 
ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢀꢇ  
ꢈꢉꢂ ꢊꢋꢁ ꢌꢍ ꢎꢄ ꢋꢈꢌꢄ ꢏ ꢐꢑ ꢋ ꢊꢂꢄꢃ ꢒ  
ꢓ ꢎꢄ ꢒꢋ ꢇ ꢔꢕꢄꢂꢄ ꢑꢋ ꢖ ꢉꢄ ꢐꢉ ꢄꢕ  
SCAS096 − FEBRUARY 1990 − REVISED APRIL 1993  
Inputs Are TTL-Voltage Compatible  
DW OR NT PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
1C  
1Q1  
1Q2  
1Q3  
1Q4  
GND  
GND  
GND  
GND  
2Q1  
2Q2  
2Q3  
2Q4  
2C  
1
28 1OC  
Bus-Structured Pinout  
2
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1CLR  
1D1  
1D2  
1D3  
1D4  
Flow-Through Architecture to Optimize  
3
PCB Layout  
4
Center-Pin V  
and GND Configurations to  
Minimize High-Speed Switching Noise  
5
CC  
6
7
EPICt (Enhanced-Performance Implanted  
V
V
CC  
CC  
8
CMOS) 1-mm Process  
9
2D1  
2D2  
2D3  
2D4  
2CLR  
2OC  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic Small-  
Outline Packages and Standard Plastic  
300-mil DIPs  
10  
11  
12  
13  
14  
description  
These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes these  
devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working  
registers.  
The dual 4-bit latch is transparent D-type. When the latch enable input (1C or 2C) is high, the (Q) outputs will  
follow the data (D) inputs in true form, according to the function table. When the latch enable input is taken low,  
the outputs will be latched. When CLR goes low, the Q outputs go low independently of enable C. The outputs  
are in a high-impedance state when OC (output control) is at a high logic level.  
The 74ACT11873 is characterized for operation from − 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
CLR  
OUTPUT  
OC  
L
C
D
X
H
L
Q
L
L
H
H
H
X
X
H
H
L
L
H
L
L
L
X
X
Q
o
Z
H
X
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢤ  
Copyright 1993, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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Fixed Point ALU