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74ACT11898

更新时间： 2024-10-03 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
11页 221K
描述
10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER

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74ACT11898 数据手册

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SCAS144 − OCTOBER 1990 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
• Inputs Are TTL-Voltage Compatible  
• AND-Gated (Enable/Disable) Serial Inputs  
• Fully Buffered Clock and Serial Inputs  
• Direct Clear  
Q
Q
Q
Q
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
C
D
B
A
Q
CLR  
A
E
• Fully Synchronous Data Transfers  
GND  
GND  
GND  
GND  
• Flow-Through Architecture Optimizes  
V
CC  
PCB Layout  
V
CC  
• Center-Pin V  
and GND Pin Configurations  
Minimize High-Speed Switching Noise  
CC  
B
Q
CLK  
F
Q
G
Q
• EPIC(Enhanced-Performance Implanted  
J
CMOS) 1-µm Process  
Q
Q
I
H
• 500-mA Typical Latch-Up Immunity at 125°C  
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
The 74ACT11898 features AND-gated serial inputs and an asynchronous clear. The gated serial inputs  
(A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets  
the first flip-flop to the low level on the rising edge of the next clock pulse. A high-level input enables the other  
input, which then determines the state of the first flip-flop. Data at the serial inputs may be changed while the  
clock is high or low provided the minimum setup and hold time requirements are met. Clocking occurs on the  
low-to-high transition of the clock input.  
The 74ACT11898 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
...  
CLR  
L
CLK  
A
X
X
H
L
B
X
X
H
X
L
Q
Q
Q
J
A
B
X
L
↑
↑
↑
L
L
L
H
Q
Q
Q
JO  
A0  
B0  
AN  
AN  
AN  
H
H
L
L
Q
Q
Q
Q
Q
Q
IN  
IN  
IN  
H
H
X
H = high level (steady state)  
X = irrelevant (any input, including transitions)  
↑ = transition from low to high level  
Q
, Q , Q = the level of Q , Q , Q respectively, before the  
A0 B0 J0  
A
B
J
indicated steady-state inputconditions were established.  
Q , Q = the level or Q or Q before the most recent ↑ transition  
n
in  
A
J
of the clock; indicates aone-bit shift.t  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
1234567...11

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