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74ACT08M PDF预览

74ACT08M

更新时间: 2024-09-14 22:53:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 175K
描述
QUAD 2-INPUT AND GATE

74ACT08M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-14
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.11
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.024 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

74ACT08M 数据手册

 浏览型号74ACT08M的Datasheet PDF文件第2页浏览型号74ACT08M的Datasheet PDF文件第3页浏览型号74ACT08M的Datasheet PDF文件第4页浏览型号74ACT08M的Datasheet PDF文件第5页浏览型号74ACT08M的Datasheet PDF文件第6页浏览型号74ACT08M的Datasheet PDF文件第7页 
74ACT08  
QUAD 2-INPUT AND GATE  
HIGH SPEED: t = 4.5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
DIP  
SOP  
74ACT08B  
74ACT08M  
V
CC  
74ACT08MTR  
74ACT08TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 08  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
All inputs and outputs are equipped with protec-  
tion circuits against static discharge, giving them  
2KV ESD immunity and transient excess voltage.  
DESCRIPTION  
The 74ACT08 is an advanced high-speed CMOS  
QUAD 2-INPUT AND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS tecnology.  
The internal circuit is composed of 2 stages  
including buffer output, which enables high noise  
immunity and stable output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/8  

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