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74AC11257PWRE4 PDF预览

74AC11257PWRE4

更新时间: 2024-11-24 04:47:27
品牌 Logo 应用领域
德州仪器 - TI 解复用器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 302K
描述
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS

74AC11257PWRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, PLASTIC, TSSOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.4Is Samacsys:N
系列:ACJESD-30 代码:R-PDSO-G20
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:MULTIPLEXER最大I(ol):0.024 A
功能数量:4输入次数:2
输出次数:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
Prop。Delay @ Nom-Sup:10.1 ns传播延迟(tpd):10.1 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74AC11257PWRE4 数据手册

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ꢀꢁ ꢂꢃ ꢄꢄꢅ ꢆꢀ  
ꢇ ꢈꢂꢉ ꢊ ꢈꢋꢌ ꢍ ꢅ ꢎꢌ ꢏꢐꢍ ꢑ ꢒ ꢄ ꢎꢌ ꢏꢐꢍ ꢉꢂꢑꢂ ꢓꢍ ꢌꢍ ꢃꢑꢒ ꢊꢔꢕ ꢈꢌꢑꢏ ꢋ ꢌꢍ ꢖꢍ ꢊ  
ꢗ ꢏꢑ ꢘ ꢙ ꢎꢓꢑꢂꢑ ꢍ ꢒ ꢈꢑ ꢋꢈ ꢑꢓ  
SCAS049C − MARCH 1989 − REVISED MAY 2004  
DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
3-State Outputs Interface Directly With  
System Bus  
Flow-Through Architecture Optimizes  
PCB Layout  
A/B  
1Y  
1A  
1B  
2A  
2B  
V
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
2Y  
CC  
GND  
GND  
GND  
GND  
3Y  
500-mA Typical Latch-Up Immunity at  
125°C  
Provides Bus Interface From Multiple  
Sources in High-Performance Systems  
CC  
V
CC  
14 3A  
13 3B  
12  
11  
4Y  
OE  
4A  
4B  
description/ordering information  
This device is designed to multiplex signals from 4-bit data sources to four output data lines in bus-organized  
systems. The 3-state outputs do not load the data lines when the output-enable (OE) input is at a high logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
T
A
PACKAGE  
TOP-SIDE MARKING  
PDIP − N  
Tube  
74AC11257N  
74AC11257N  
Tube  
74AC11257DW  
74AC11257DWR  
74AC11257DBR  
74AC11257PW  
74AC11257PWR  
SOIC − DW  
SSOP − DB  
AC11257  
AE257  
Tape and reel  
Tape and reel  
Tube  
−40°C to 85°C  
TSSOP − PW  
AE257  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
DATA  
SELECT  
A/B  
Y
OE  
A
X
L
B
X
X
X
L
H
L
L
L
L
X
L
Z
L
L
H
X
X
H
L
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢑꢥ  
Copyright 2004, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢣꢥ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74AC11257PWRE4 替代型号

型号 品牌 替代类型 描述 数据表
74AC11257PWE4 TI

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