Datasheet > 74AC11286_11

74AC11286_11

更新时间： 2024-11-10 02:58:35

品牌	Logo	应用领域
德州仪器 - TI		驱动
页数	文件大小	规格书
7页	96K
描述
9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

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74AC11286_11 数据手册

74AC11286

9-BIT PARITY GENERATOR/CHECKER

WITH BUS DRIVER PARITY I/O PORTS

SCAS068A – AUGUST 1988 – REVISED APRIL 1993

D OR N PACKAGE

(TOP VIEW)

• Generates Either Odd or Even Parity for

Nine Data Lines

• Cascadable for n-Bits Parity

• Direct Bus Connection for Parity

Generation or for Checking by Using the

Parity I/O Port

PARITY I/O

GND

PARITY ERROR

• Flow-Through Architecture Optimizes

PCB Layout

XMIT

• Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

• EPIC (Enhanced-Performance Implanted

CMOS) 1- m Process

• 500-mA Typical Latch-Up Immunity

at 125°C

• Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a

bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by

cascading.

TheXMITcontrolinputisimplementedspecificallytoaccommodatecascading. WhentheXMITislow, theparity

tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels.

When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either

an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd

number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port will remain in the high-impedance state during power

up or power down to prevent bus glitches.

The 74AC11286 is characterized for operation from – 40°C to 85°C.

FUNCTION TABLE

NUMBER OF INPUTS

(A THRU I) THAT

ARE HIGH

PARITY

ERROR

OUTPUT

XMIT

INPUT

PARITY

I/O

0, 2, 4, 6, 8

1, 3, 5, 7, 9

0, 2, 4, 6, 8

1, 3, 5, 7, 9

h — high input level

H — high output level

l — low input level

L — low output level

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与74AC11286_11相关器件

型号	品牌	获取价格	描述	数据表
74AC11286D	NXP	获取价格	9-bit odd/even parity generator/checker with bus drive l/O port
74AC11286D	PHILIPS	获取价格	Parity Generator/Checker, CMOS, PDSO14
74AC11286D	YAGEO	获取价格	Parity Generator/Checker, AC Series, 9-Bit, True Output, CMOS, PDSO14
74AC11286D	TI	获取价格	9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS
74AC11286DR	TI	获取价格	9-Bit Parity Generators/Checkers With Bus Driver Parity I/O Port 14-SOIC -40 to 85
74AC11286D-T	YAGEO	获取价格	Parity Generator/Checker, AC Series, 9-Bit, True Output, CMOS, PDSO14
74AC11286J	TI	获取价格	暂无描述
74AC11286N	TI	获取价格	9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS
74AC11286N	YAGEO	获取价格	Parity Generator/Checker, AC Series, 9-Bit, True Output, CMOS, PDIP14
74AC11286N	PHILIPS	获取价格	Parity Generator/Checker, CMOS, PDIP14

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