54AC11253, 74AC11253
DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCAS041A – MAY 1988 – REVISED APRIL 1993
54AC11253 . . . J PACKAGE
74AC11253 . . . D OR N PACKAGE
(TOP VIEW)
• Permits Multiplexing From N Lines to
One Line
• Performs Parallel-to-Serial Conversion
• Flow-Through Architecture Optimizes
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1C0
1C1
1C2
1C3
A
B
1Y
GND
2Y
1G
PCB Layout
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
CC
• EPIC (Enhanced-Performance Implanted
V
CC
CMOS) 1- m Process
2C0
2C1
2C2
2G
2C3
• Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
54AC11253 . . . FK PACKAGE
(TOP VIEW)
description
Each of these data selectors/multiplexers
contains inverters and drivers to supply full binary
decoding data selection to the AND-OR gates.
Separate output control inputs are provided for
each of the two four-line sections.
3
2
1
20 19
18
2C1
2C2
NC
1C1
1C0
NC
A
4
5
6
7
8
17
16
15
14
2C3
2G
The three-state outputs can interface with and
drive data lines of bus-organized systems. With
all but one of the common outputs disabled (at a
high-impedance state), the low-impedance of the
single enabled output will drive the bus line to a
high or low logic level. Each output has its own
strobe (G). The output is disabled when its strobe
is high.
B
9 10 11 12 13
NC – No internal connection
†
logic symbol
The 54AC11253 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74AC11253 is characterized for
operation from – 40°C to 85°C.
1
2
0
1
0
3
A
B
G
MUX
6
1G
1C0
1C1
1C2
1C3
2G
EN
0
FUNCTION TABLE
16
15
14
13
7
SELECT
INPUTS
OUTPUT
CONTROL
G
DATA INPUTS
OUTPUT
Y
3
5
1
2
3
1Y
2Y
B
X
L
A
X
L
C0 C1 C2 C3
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
Z
L
11
10
9
L
L
H
X
X
X
X
X
X
H
L
2C0
2C1
2C2
2C3
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
H
8
L
H
X
X
H
L
†
H
H
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
H
H
Address inputs A and B are common to both sections.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265