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74ABT821D,602 PDF预览

74ABT821D,602

更新时间: 2024-11-18 14:46:59
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
16页 143K
描述
74ABT821 - 10-bit D-type flip-flop; positive-edge trigger; 3-state SOP 24-Pin

74ABT821D,602 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOP包装说明:SOP, SOP24,.4
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.37
其他特性:POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; WITH POWER-UP RESET系列:ABT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:125000000 Hz
最大I(ol):0.064 A湿度敏感等级:1
位数:10功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):38 mA
传播延迟(tpd):6.7 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

74ABT821D,602 数据手册

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74ABT821  
10-bit D-type flip-flop; positive-edge trigger; 3-state  
Rev. 5 — 7 November 2011  
Product data sheet  
1. General description  
The 74ABT821 high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT821 bus interface register is designed to eliminate the extra packages required  
to buffer existing registers and provide extra data width for wider data/address paths of  
buses carrying parity.  
The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A.  
The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers.  
The device is controlled by the clock (CP) and output enable (OE) control gates.  
The register is fully edge triggered. The state of each D input, one set-up time before the  
LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.  
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS  
memories, or MOS microprocessors.  
The active LOW output enable (OE) controls all ten 3-state buffers independent of the  
register operation. When OE is LOW, the data in the register appears at the outputs.  
When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will  
neither drive nor load the bus.  
2. Features and benefits  
High-speed parallel registers with positive-edge triggered D-type flip-flops  
Ideal where high speed, light loading, or increased fan-in are required with MOS  
microprocessors  
Output capability: +64 mA and 32 mA  
Power-on 3-state  
Power-on reset  
Latch-up protection exceeds 500 mA per JESD78B class II level A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
 
 

74ABT821D,602 替代型号

型号 品牌 替代类型 描述 数据表
74ABT821D,623 NXP

完全替代

74ABT821 - 10-bit D-type flip-flop; positive-edge trigger; 3-state SOP 24-Pin
74ABT821D NXP

完全替代

10-bit D-type flip-flop; positive-edge trigger 3-State

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