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74ABT823D PDF预览

74ABT823D

更新时间: 2024-02-28 01:05:29
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器触发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
7页 80K
描述
9-bit D-type flip-flop with reset and enable 3-State

74ABT823D 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24
针数:24Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N其他特性:WITH CLEAR AND CLOCK ENABLE
系列:ABTJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:125000000 Hz最大I(ol):0.064 A
湿度敏感等级:1位数:9
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):34 mA
传播延迟(tpd):6.8 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:4.4 mmBase Number Matches:1

74ABT823D 数据手册

 浏览型号74ABT823D的Datasheet PDF文件第2页浏览型号74ABT823D的Datasheet PDF文件第3页浏览型号74ABT823D的Datasheet PDF文件第4页浏览型号74ABT823D的Datasheet PDF文件第5页浏览型号74ABT823D的Datasheet PDF文件第6页浏览型号74ABT823D的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
9-bit D-type flip-flop with reset and enable  
(3-State)  
74ABT823  
FEATURES  
DESCRIPTION  
The 74ABT823 Bus interface Register is designed to eliminate the  
extra packages required to buffer existing registers and provide  
extra data width for wider data/address paths of buses carrying  
parity.  
High speed parallel registers with positive edge-triggered D-type  
flip-flops  
Ideal where high speed, light loading, or increased fan-in are  
required with MOS microprocessors  
The 74ABT823 is a 9-bit wide buffered register with Clock Enable  
(CE) and Master Reset (MR) which are ideal for parity bus  
interfacing in high microprogrammed systems.  
Output capability: +64mA/–32mA  
Latch-up protection exceeds 500mA per Jedec Std 17  
The register is fully edge-triggered. The state of each D input, one  
set-up time before the Low-to-High clock transition is transferred to  
the corresponding flip-flop’s Q output.  
ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
and 200 V per Machine Model  
Power-up 3-State  
Power-up Reset  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
CP to Qn  
PLH  
PHL  
C = 50pF; V = 5V  
4.4  
4
ns  
pF  
pF  
nA  
L
CC  
C
Input capacitance  
V = 0V or V  
I CC  
IN  
Outputs disabled;  
= 0V or V  
C
Output capacitance  
Total supply current  
7
OUT  
CCZ  
V
O
CC  
I
Outputs disabled; V =5.5V  
500  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74ABT823 N  
DWG NUMBER  
SOT222-1  
24-Pin Plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT823 N  
74ABT823 D  
74ABT823 DB  
74ABT823 PW  
24-Pin plastic SO  
74ABT823 D  
SOT137-1  
24-Pin Plastic SSOP Type II  
24-Pin Plastic TSSOP Type I  
74ABT823 DB  
74ABT823PW DH  
SOT340-1  
SOT355-1  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN NUMBER  
SYMBOL  
FUNCTION  
Output enable input  
(active-Low)  
1
OE  
D0-D8  
Q0-Q8  
CP  
24  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
V
CC  
23 Q0  
22 Q1  
21 Q2  
20 Q3  
19 Q4  
18 Q5  
17 Q6  
16 Q7  
2, 3, 4, 5, 6,  
7, 8, 9, 10  
Data inputs  
23, 22, 21, 20,  
19,18, 17, 16, 15  
Data outputs  
Clock pulse input (active  
rising edge)  
13  
14  
11  
Clock enable input  
(active-Low)  
CE  
Master reset input  
(active-Low)  
MR  
D8 10  
MR 11  
15  
14  
13  
Q8  
CE  
CP  
12  
24  
GND  
Ground (0V)  
GND 12  
V
CC  
Positive supply voltage  
TOP VIEW  
SA00227  
1
1995 Sep 06  
853–1617 15703  

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