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74ABT16646CSSCX_NL PDF预览

74ABT16646CSSCX_NL

更新时间: 2024-10-28 21:08:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
9页 84K
描述
Registered Bus Transceiver, ABT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO56, 0.300 INCH, LEAD FREE, MO-118, SSOP-56

74ABT16646CSSCX_NL 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknown风险等级:5.67
其他特性:WITH DIRECTION CONTROL系列:ABT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.415 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
传播延迟(tpd):10 ns认证状态:Not Qualified
座面最大高度:2.74 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74ABT16646CSSCX_NL 数据手册

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October 1993  
Revised November 1999  
74ABT16646  
16-Bit Transceivers and Registers with 3-STATE Outputs  
General Description  
Features  
The ABT16646 consists of bus transceiver circuits with 3-  
STATE, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus  
or from the internal registers. Data on the A or B bus will be  
clocked into the registers as the appropriate clock pin goes  
to a high logic level. Control OE and direction pins are pro-  
vided to control the transceiver function. In the transceiver  
mode, data present at the high impedance port may be  
stored in either the A or the B register or in both. The select  
controls can multiplex stored and real-time (transparent  
mode) data. The direction control determines which bus  
will receive data when the enable control OE is Active  
LOW. In the isolation mode (control OE HIGH), A data may  
be stored in the B register and/or B data may be stored in  
the A register.  
Independent registers for A and B buses  
Multiplexed real-time and stored data  
A and B output sink capability of 64 mA, source  
capability of 32 mA  
Guaranteed latchup protection  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Ordering Code:  
Order Number  
74ABT16646CSSC  
74ABT16646CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
A0A15  
B0B15  
Data Register A Inputs/  
3-STATE Outputs  
Data Register B Inputs/  
3-STATE Outputs  
CPABn, CPBAn  
SABn, SBAn  
OEn  
Clock Pulse Inputs  
Select Inputs  
Output Enable Input  
Direction Control Input  
DIR  
© 1999 Fairchild Semiconductor Corporation  
DS011644  
www.fairchildsemi.com  

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