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74ABT16652CMTDX PDF预览

74ABT16652CMTDX

更新时间: 2024-11-22 21:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
9页 94K
描述
16-Bit Transceivers and Registers with 3-STATE Outputs

74ABT16652CMTDX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP56,.3,20针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.22Is Samacsys:N
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ABT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:14 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.064 A
湿度敏感等级:2位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):60 mA
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74ABT16652CMTDX 数据手册

 浏览型号74ABT16652CMTDX的Datasheet PDF文件第2页浏览型号74ABT16652CMTDX的Datasheet PDF文件第3页浏览型号74ABT16652CMTDX的Datasheet PDF文件第4页浏览型号74ABT16652CMTDX的Datasheet PDF文件第5页浏览型号74ABT16652CMTDX的Datasheet PDF文件第6页浏览型号74ABT16652CMTDX的Datasheet PDF文件第7页 
April 1993  
Revised January 1999  
74ABT16652  
16-Bit Transceivers and Registers with 3-STATE Outputs  
General Description  
Features  
Independent registers for A and B buses  
Multiplexed real-time and stored data  
Separate control logic for each byte  
The ABT16652 consists of sixteen bus transceiver circuits  
with D-type flip-flops, and control circuitry arranged for mul-  
tiplexed transmission of data directly from the input bus or  
from the internal registers. Each byte has separate control  
inputs which can be shorted together for full 16-bit opera-  
tion. Data on the A or B bus will be clocked into the regis-  
ters as the appropriate clock pin goes to HIGH logic level.  
Output Enable pins (OEAB, OEBA) are provided to control  
the transceiver function.  
A and B output sink capability of 64 mA, source  
capability of 32 mA  
Guaranteed output skew  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Ordering Code:  
Order Number  
74ABT16652CSSC  
74ABT16652CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pin Descriptions  
Connection Diagram  
Pin Names  
Descriptions  
A0–A16  
B0–B16  
Data Register A Inputs/  
3-STATE Outputs  
Data Register B Inputs/  
3-STATE Outputs  
CPABn, CPBAn  
SABn, SBAn  
Clock Pulse Inputs  
Select Inputs  
OEABn, OEBAn  
Output Enable Inputs  
© 1999 Fairchild Semiconductor Corporation  
DS011599.prf  
www.fairchildsemi.com  

74ABT16652CMTDX 替代型号

型号 品牌 替代类型 描述 数据表
74ABT16652CMTD FAIRCHILD

完全替代

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