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74ABT16821ADG PDF预览

74ABT16821ADG

更新时间: 2024-11-23 13:00:47
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
16页 145K
描述
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74ABT16821ADG 数据手册

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74ABT16821A  
20-bit bus-interface D-type flip-flop; positive-edge trigger;  
3-state  
Rev. 03 — 16 March 2010  
Product data sheet  
1. General description  
The 74ABT16821A high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT16821A has two 10-bit, edge-triggered registers, with each register coupled to  
a 3-state output buffer. The two sections of each register are controlled independently by  
the clock (nCP) and output enable (nOE) control gates.  
Each register is fully edge triggered. The state of each D input, one set-up time before the  
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.  
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS  
memories, or MOS microprocessors.  
The active-LOW output enable (nOE) controls all ten 3-state buffers independent of the  
register operation. When nOE is LOW, the data in the register appears at the outputs.  
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will  
neither drive nor load the bus.  
2. Features and benefits  
„ 20-bit positive-edge triggered register  
„ Multiple VCC and GND pins minimize switching noise  
„ Live insertion and extraction permitted  
„ Output capability: +64 mA and 32 mA  
„ Power-up 3-state  
„ Power-up reset  
„ Latch-up protection exceeds 500 mA per JESD78B class II level A  
„ ESD protection:  
‹ HBM JESD22-A114F exceeds 2000 V  
‹ MM JESD22-A115-A exceeds 200 V  

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