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74ABT16652CMTD PDF预览

74ABT16652CMTD

更新时间: 2024-10-27 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 94K
描述
16-Bit Transceivers and Registers with 3-STATE Outputs

74ABT16652CMTD 数据手册

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April 1993  
Revised January 1999  
74ABT16652  
16-Bit Transceivers and Registers with 3-STATE Outputs  
General Description  
Features  
Independent registers for A and B buses  
Multiplexed real-time and stored data  
Separate control logic for each byte  
The ABT16652 consists of sixteen bus transceiver circuits  
with D-type flip-flops, and control circuitry arranged for mul-  
tiplexed transmission of data directly from the input bus or  
from the internal registers. Each byte has separate control  
inputs which can be shorted together for full 16-bit opera-  
tion. Data on the A or B bus will be clocked into the regis-  
ters as the appropriate clock pin goes to HIGH logic level.  
Output Enable pins (OEAB, OEBA) are provided to control  
the transceiver function.  
A and B output sink capability of 64 mA, source  
capability of 32 mA  
Guaranteed output skew  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Ordering Code:  
Order Number  
74ABT16652CSSC  
74ABT16652CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pin Descriptions  
Connection Diagram  
Pin Names  
Descriptions  
A0–A16  
B0–B16  
Data Register A Inputs/  
3-STATE Outputs  
Data Register B Inputs/  
3-STATE Outputs  
CPABn, CPBAn  
SABn, SBAn  
Clock Pulse Inputs  
Select Inputs  
OEABn, OEBAn  
Output Enable Inputs  
© 1999 Fairchild Semiconductor Corporation  
DS011599.prf  
www.fairchildsemi.com  

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