74LS193

更新时间： 2024-01-05 06:54:54

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器时钟
页数	文件大小	规格书
7页	77K
描述
Synchronous 4-Bit Binary Counter with Dual Clock

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技术参数
数据手册

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74LS193 技术参数

生命周期：	Contact Manufacturer	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.77
Is Samacsys：	N	逻辑集成电路类型：	BINARY COUNTER
Base Number Matches：	1

74LS193 数据手册

September 1986

Revised March 2000

DM74LS193

Synchronous 4-Bit Binary Counter with Dual Clock

of the count and load inputs. The clear, count, and load

inputs are buffered to lower the drive requirements of clock

drivers, etc., required for long words.

General Description

The DM74LS193 circuit is a synchronous up/down 4-bit

binary counter. Synchronous operation is provided by hav-

These counters were designed to be cascaded without the

ing all flip-flops clocked simultaneously, so that the outputs

need for external circuitry. Both borrow and carry outputs

change together when so instructed by the steering logic.

are available to cascade both the up and down counting

This mode of operation eliminates the output counting

functions. The borrow output produces a pulse equal in

spikes normally associated with asynchronous (ripple-

width to the count down input when the counter underflows.

clock) counters.

Similarly, the carry output produces a pulse equal in width

The outputs of the four master-slave flip-flops are triggered

to the count down input when an overflow condition exists.

by a LOW-to-HIGH level transition of either count (clock)

The counters can then be easily cascaded by feeding the

input. The direction of counting is determined by which

borrow and carry outputs to the count down and count up

count input is pulsed while the other count input is held

inputs respectively of the succeeding counter.

HIGH.

The counter is fully programmable; that is, each output may

Features

be preset to either level by entering the desired data at the

■ Fully independent clear input

inputs while the load input is LOW. The output will change

independently of the count pulses. This feature allows the

counters to be used as modulo-N dividers by simply modi-

fying the count length with the preset inputs.

■ Synchronous operation

■ Cascading circuitry provided internally

■ Individual preset each flip-flop

A clear input has been provided which, when taken to a

high level, forces all outputs to the low level; independent

Ordering Code:

Order Number Package Number

Package Description

DM74LS193M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DM74LS193N

N16E

Connection Diagram

DS006406

www.fairchildsemi.com

12 3 4 5 6 7

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