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73K324BL-IHR/F PDF预览

73K324BL-IHR/F

更新时间： 2024-01-19 05:13:14
品牌 Logo 应用领域
TERIDIAN 调制解调器
页数 文件大小 规格书
34页 205K
描述
Single-Chip Modem w/ Integrated Hybrid

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中文翻译

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73K324BL-IHR/F 技术参数

生命周期：Transferred包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.04其他特性：FULL DUPLEX
数据速率：2.4 MbpsJESD-30 代码：R-PDIP-T22
功能数量：1端子数量：22
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
最大压摆率：25 mA标称供电电压：5 V
表面贴装：NO电信集成电路类型：MODEM
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子位置：DUALBase Number Matches：1

73K324BL-IHR/F 数据手册

 浏览型号73K324BL-IHR/F的Datasheet PDF文件第3页浏览型号73K324BL-IHR/F的Datasheet PDF文件第4页浏览型号73K324BL-IHR/F的Datasheet PDF文件第5页浏览型号73K324BL-IHR/F的Datasheet PDF文件第7页浏览型号73K324BL-IHR/F的Datasheet PDF文件第8页浏览型号73K324BL-IHR/F的Datasheet PDF文件第9页 
73K324BL  
CCITT V.22bis,V.23,V.22,V.21, Bell 212A  
Single-Chip Modem w/ Integrated Hybrid  
DATA SHEET  
PARALLEL MICROPROCESSOR INTERFACE (continued)  
NAME  
PIN  
TYPE  
DESCRIPTION  
WR  
14  
I
WRITE: A low on this informs the 73K324BL that data is  
available on AD0-AD7 for writing into an internal register.  
Data is latched on the rising edge of WR. No data is written  
unless both WR and the latched CS are low.  
SERIAL MICROPROCESSOR CONTROL INTERFACE MODE  
NAME  
PIN  
TYPE  
DESCRIPTION  
AD0-AD2  
5-7  
I
REGISTER ADDRESS SELECTION: These lines carry  
register addresses and should be valid during any read or  
write operation.  
DATA (AD7)  
12  
15  
I/O  
I
SERIAL CONTROL DATA: Data for a read/write operation is  
clocked in or out on the falling edge of the EXCLK pin. The  
direction of data flow is controlled by the RD pin. RD low  
outputs data. RD high inputs data.  
RD  
READ: A low on this input informs the 73K324BL that data or  
status information is being read by the processor. The falling  
edge of the RD signal will initiate a read from the addressed  
register. The RD signal must continue for eight falling edges  
of EXCLK in order to read all eight bits of the referenced  
register. Read data is provided LSB first. Data will not be  
output unless the RD signal is active.  
WR  
14  
I
WRITE: A low on this input informs the 73K324BL that data  
or status information has been shifted in through the DATA  
pin and is available for writing to an internal register. The  
normal procedure for a write is to shift in data LSB first on the  
DATA pin for eight consecutive falling edges of EXCLK and  
then to pulse WR low. Data is written on the rising edge of  
WR.  
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes  
DATA and AD0, AD1 and AD2 become the register address.  
Page: 6 of 34  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 6.1  
1...3456789...34

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