Datasheet > 电信电路 > 调制解调器> 73K324BL-IHR/F

73K324BL-IHR/F

更新时间： 2024-02-03 19:31:16

品牌	Logo	应用领域
TERIDIAN		调制解调器
页数	文件大小	规格书
34页	205K
描述
Single-Chip Modem w/ Integrated Hybrid

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技术参数
数据手册

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73K324BL-IHR/F 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.04	其他特性：	FULL DUPLEX
数据速率：	2.4 Mbps	JESD-30 代码：	R-PDIP-T22
功能数量：	1	端子数量：	22
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
最大压摆率：	25 mA	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子位置：	DUAL	Base Number Matches：	1

73K324BL-IHR/F 数据手册

73K324BL

CCITT V.22bis,V.23,V.22,V.21, Bell 212A

Single-Chip Modem w/ Integrated Hybrid

DATA SHEET

DTE USER

NAME

TYPE

DESCRIPTION

EXCLK

EXTERNAL CLOCK: This signal is used in synchronous

transmission when the external timing option has been

selected. In the external timing mode the rising edge of

EXCLK is used to strobe synchronous DPSK transmit data

applied to on the TXD pin. Also used for serial control

interface.

RXCLK

RECEIVE CLOCK: The falling edge of this clock output is

coincident with the transitions in the serial received data

output. The rising edge of RXCLK can be used to latch the

valid output data. RXCLK will be valid as long as a carrier is

present.

RXD

RECEIVED DATA OUTPUT: Serial receive data is available

on this pin. The data is always valid on the rising edge of

RXCLK when in synchronous mode. RXD will output

constant marks if no carrier is detected.

TXCLK

TRANSMIT CLOCK: This signal is used in synchronous

transmission to latch serial input data on the TXD pin. Data

must be provided so that valid data is available on the rising

edge of the TXCLK. The transmit clock is derived from

different sources depending upon the synchronization mode

selection. In internal mode the clock is generated internally.

In external mode TXCLK is phase locked to the EXCLK pin.

In slave mode TXCLK is phase locked to the RXCLK pin.

TXCLK is always active.

TXD

TRANSMIT DATA INPUT: Serial data for transmission is

applied on this pin. In synchronous modes, the data must be

valid on the rising edge of the TXCLK clock. In asynchronous

modes (1200/600 bps or 300/1200 baud) no clocking is

necessary. DPSK data must be 1200/600 bps +1%, -2.5% or

+2.3%, -2.5 % in extended over speed mode.

Page: 7 of 34

Rev 6.1

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73K324L-28IH/F	TERIDIAN	Single-Chip Modem	获取价格
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73K324L-IGT	ETC	CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem	获取价格