IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
PINDESCRIPTION
SYMBOL
A0-14
C32i
NAME
Address 0 to 14
Clock
I/O
DESCRIPTION
Theseaddresslinesaccessallinternalmemories.
I
I
I
Serialclockforshiftingdatain/outontheserialdatastream.Thisinputacceptsa32.768MHzclock.
ThisactiveLOWinputisusedbyamicroprocessortoactivatethemicroprocessorportofIDT72V73250.
CS
D0-15
DS
ChipSelect
Data Bus 0-15
DataStrobe
I/O Thesepinsarethedatabitsofthemicroprocessorport.
I
ThisactiveLOWinputworksinconjunctionwith CStoenablethereadandwriteoperationsandsetsthe
data bus lines (D0-D15).
DTA
DataTransfer
Acknowledgment
O
Indicatesthatadatabustransferiscomplete. Whenthebuscycleends, thispindrivesHIGHandthengoes
high-impedance, allowingforfasterbuscycleswithaweakerpull-upresistor. Apull-upresistorisrequired
to hold a HIGH level when the pin is in high-impedance.
FE
Frame Evaluation
FramePulse
I
I
This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.
F32i
Thisinputacceptsandautomaticallyidentifiesframesynchronizationsignalsformattedaccordingto
ST-BUS®andGCIspecifications.
GND
ODE
Ground
GroundRail
OutputDriveEnable
I
I
ThisistheoutputenablecontrolfortheTXserialoutputs.WhentheODEinputisLOWandtheOutputStand
BybitoftheControlRegisterisLOW,allTXoutputsareinahigh-impedancestate.IfthisinputisHIGH,theTX
outputdriversareenabled.However,eachchannelmaystillbeputintoahigh-impedancestatebyusingthe
per-channelcontrolbitsintheConnectionMemory.
RESET
DeviceReset
Read/Write
ThisinputputstheIDT72V73250intoaresetstatethatclearsthedeviceinternalcounters,registersand
brings TX0-15 and D0-D15 into a high-impedance state. The RESET pin must be held LOW for a minimum
of 20ns to properly reset the device.
R/W
I
I
Thisinputcontrolsthedirectionofthedatabuslines(D0-D15)duringamicroprocessoraccess.
Serial data input stream. These streams have a data rate of 32.768 Mb/s.
RX0-15 DataStream
Input 0 to 15
TCK
TDI
TestClock
I
I
ProvidestheclocktotheJTAGtestlogic.
Test Serial Data In
JTAGserialtestinstructionsanddataareshiftedinonthispin. ThispinispulledHIGHbyaninternalpull-up
when not driven.
TDO
TMS
TRST
TestSerialDataOut
TestModeSelect
TestReset
O
I
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
JTAGsignalthatcontrolsthestatetransitionsoftheTAPcontroller.ThispinispulledHIGHbyaninternal
pull-up when not driven.
I
AsynchronouslyinitializestheJTAGTAPcontrollerbyputtingitintheTest-Logic-Resetstate.Thispinis
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
toensurethattheIDT72V73250isinthenormalfunctionalmode.
TX0-7
TX Output 0 to 7
(Three-StateOutputs)
O
O
Serial data output stream. These streams have a data rate of 32.768 Mb/s.
TX8-15/ TX Output 8 to 15/
OEI0-7
Whenall16outputstreamsareselectedviaControlRegister,thesepinsaretheoutputstreamsTX8toTX15
andoperateat32.768Mb/s.Whenoutputenablefunctionisselected,thesepinsreflecttheactiveorhigh-
impedancestatusforthecorrespondingoutputstreamOutputEnableIndication0-7.
OutputEnable
Indication0-7
(Three-StateOutputs)
VCC
VCC
+3.3 Volt Power Supply.
4
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