72V73273BBBLANK

更新时间： 2024-11-26 12:50:15

品牌	Logo	应用领域
艾迪悌 - IDT		配套器件
页数	文件大小	规格书
36页	1542K
描述
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS

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72V73273BBBLANK 数据手册

3.3 VOLT TIME SLOT INTERCHANGE

DIGITAL SWITCH WITH RATE

MATCHING 32,768 ^X32,768 CHANNELS

IDT72V73273

•

Selectable Synchronous and Asynchronous microprocessor

bus timing modes

IEEE-1149.1 (JTAG) Test Port

208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)

Operating Temperature Range -40°C to +85°C

FEATURES:

•

Up to 64 serial input and output streams

Maximum 32,768 x 32,768 channel non-blocking switching

Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,

16.384Mb/s or 32.768Mb/s

•

Rate matching capability: rate selectable on both RX and TX

in eight groups of 8 streams

Optional Output Enable Indication Pins for external driver

High-Z control

Per-channel Variable Delay Mode for low-latency applications

Per-channel Constant Delay Mode for frame integrity applications

Enhanced Block programming capabilities

TX/RX Internal Bypass

Automatic identification of ST-BUS and GCI serial streams

Per-stream frame delay offset programming

Per-channel High-Impedance output control

Per-channelprocessormodetoallowmicroprocessorwritestoTX

streams

DESCRIPTION:

TheIDT72V73273hasanon-blockingswitchcapacityof 32,768x32,768

channelsat32.768Mb/s. With64inputsand64outputs,programmableper

streamcontrol, andavarietyofoperatingmodestheIDT72V73273is

designed for the TDM time slot interchange function in either voice or data

applications.

•

Some of the main features of the IDT72V73273 are LOW power 3.3 Volt

operation,automaticST-BUS^®/GCIsensing,memoryblockprogramming,

simplemicroprocessorinterface,JTAGTestAccessPort(TAP)andper

stream programmable input offset delay, variable or constant throughput

modes,outputenableandprocessormode,BERtesting, bypassmode,and

advancedblockprogramming.

•

Bit Error Rate Testing (BERT) for testing

Direct microprocessor access to all internal memories

FUNCTIONALBLOCKDIAGRAM

RESET

VCC

GND

ODE

RX0-7

TX0-TX7

TX8-15/OEI0-7

RX8-15

Data Memory

MUX

RX16-23

TX16-23

RX24-31

RX32-39

RX40-47

RX48-55

RX56-63

Receive

Serial Data

Streams

TX24-31/OEI16-23

Transmit

Serial Data

Streams

TX32-39

Connection

Memory

TX40-47/OEI32-39

Internal

Registers

TX48-55

TX56-63/OEI48-55

JTAG Port

Timing Unit

Microprocessor Interface

C32i F32i

A0-A15

BEL

CS R/W

DTA/

BEH

S/A

TMS TDI TCKTDO

TRST

D0-D15

6140 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS isatrademarkofMitelCorp.

February 9, 2009

DSC-6140/4

12 3 4 5 6 7...36

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