Datasheet > 72V73263DR

72V73263DR

更新时间： 2024-11-26 20:56:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
37页	309K
描述
Telecom IC

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中文翻译

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技术参数
数据手册

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72V73263DR 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

72V73263DR 数据手册

3.3 VOLT TIME SLOT INTERCHANGE

DIGITAL SWITCH WITH RATE

IDT72V73263

MATCHING 16,384 X 16,384 CHANNELS

•

Selectable Synchronous and Asynchronous Microprocessor

bus timing modes

IEEE-1149.1 (JTAG) Test Port

Availablein208-pin(28mmx28mm)PlasticQuadFlatpack(PQFP)

and 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)

Operating Temperature Range -40°C to +85°C

FEATURES:

•

Up to 64 serial input and output streams

•

Maximum 16,384 x 16,384 channel non-blocking switching

Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,

16.384Mb/s or 32.768Mb/s

•

Rate matching capability: rate selectable on both RX and TX

in eight groups of 8 streams

Optional Output Enable Indication Pins for external driver

High-Z control

DESCRIPTION:

TheIDT72V73263hasanon-blockingswitchcapacityof 16,384x16,384

channelsat32.768Mb/s.With64inputsand64outputs,programmableper

streamcontrol,andavarietyofoperatingmodes theIDT72V73263is

designedforthe TDMtime slotinterchange functionineithervoice ordata

applications.

•

Per-channel Variable Delay Mode for low-latency applications

Per-channel Constant Delay Mode for frame integrity applications

Enhanced Block programming capabilities

TX/RX Internal Bypass

Automatic identification of ST-BUS^and GCI serial streams

Per-stream frame delay offset programming

Per-channel High-Impedance output control

Per-channelprocessormodetoallowmicroprocessor writes toTX

streams

Some of the main features of the IDT72V73263 are LOW power 3.3 Volt

operation,automaticST-BUS^®/GCIsensing,memoryblockprogramming,

simplemicroprocessorinterface,JTAGTestAccessPort(TAP)andper

stream programmable input offset delay, variable or constant throughput

modes,outputenableandprocessormode,BERtesting, bypassmode,and

advancedblockprogramming.

•

Bit Error Rate Testing (BERT) for testing

Direct microprocessor access to all internal memories

FUNCTIONALBLOCKDIAGRAM

RESET

VCC

GND

ODE

RX0-7

TX0-TX7

TX8-15/OEI0-7

RX8-15

Data Memory

MUX

RX16-23

TX16-23

RX24-31

RX32-39

RX40-47

RX48-55

RX56-63

Receive

Serial Data

Streams

TX24-31/OEI16-23

Transmit

Serial Data

Streams

TX32-39

Connection

Memory

TX40-47/OEI32-39

Internal

Registers

TX48-55

TX56-63/OEI48-55

JTAG Port

Timing Unit

Microprocessor Interface

C32i F32i

A0-A15

BEL

CS R/W

DTA/

BEH

S/A

TMS TDI TCKTDO

TRST

D0-D15

6160 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS^isatrademarkofMitelCorp.

OCTOBER 2003

DSC-6160/3

12 3 4 5 6 7...37

中文翻译

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与72V73263DR相关器件

型号	品牌	获取价格	描述	数据表
72V73273	RENESAS	获取价格	32K X 32K TSI, 64 I/O at 2/4/8/16 or 32Mbps, Rate-Matching, 3.3V
72V73273BB	IDT	获取价格	暂无描述
72V73273BBBLANK	IDT	获取价格	3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
72V73273DR	IDT	获取价格	Telecom IC, PQFP208
72V801L10PFG	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO
72V801L10PFG8	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO
72V801L10PFGI	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO
72V801L10PFGI8	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO
72V801L10TFG	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO
72V801L10TFG8	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO

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