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72V3650L7-5PFG8 PDF预览

72V3650L7-5PFG8

更新时间: 2024-01-14 00:36:19
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
46页 311K
描述
FIFO, 2KX36, 5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128

72V3650L7-5PFG8 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:LFQFP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.71Is Samacsys:N
最长访问时间:5 ns其他特性:RETRANSMIT; AUTO POWER DOWN; ASYNCHRONOUS MODE IS ALSO POSSIBLE
周期时间:7.5 nsJESD-30 代码:R-PQFP-G128
长度:20 mm内存密度:73728 bit
内存宽度:36功能数量:1
端子数量:128字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1.6 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

72V3650L7-5PFG8 数据手册

 浏览型号72V3650L7-5PFG8的Datasheet PDF文件第2页浏览型号72V3650L7-5PFG8的Datasheet PDF文件第3页浏览型号72V3650L7-5PFG8的Datasheet PDF文件第4页浏览型号72V3650L7-5PFG8的Datasheet PDF文件第5页浏览型号72V3650L7-5PFG8的Datasheet PDF文件第6页浏览型号72V3650L7-5PFG8的Datasheet PDF文件第7页 
3.3VHIGH-DENSITYSUPERSYNCII36-BITFIFO  
1,024 x 36, 2,048 x 36  
4,096 x 36, 8,192 x 36  
16,384 x 36, 32,768 x 36  
IDT72V3640,IDT72V3650  
IDT72V3660,IDT72V3670  
IDT72V3680,IDT72V3690  
Zero latency retransmit  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
FEATURES:  
Choose among the following memory organizations:Commercial  
IDT72V3640  
IDT72V3650  
IDT72V3660  
IDT72V3670  
IDT72V3680  
IDT72V3690  
1,024 x 36  
2,048 x 36  
4,096 x 36  
8,192 x 36  
16,384 x 36  
32,768 x 36  
Partial Reset clears data, but retains programmable settings  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
JTAG port, provided for Boundary Scan function (PBGA Only)  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic  
Ball Grid Array (PBGA) (with additional features)  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Up to 166 MHz Operation of the Clocks  
UserselectableAsynchronousreadand/orwriteports(PBGAOnly)  
User selectable input and output port bus-sizing  
- x36 in to x36 out  
- x36 in to x18 out  
- x36 in to x9 out  
- x18 in to x36 out  
- x9 in to x36 out  
Pin to Pin compatible to the higher density of IDT72V36100 and  
IDT72V36110  
Big-Endian/Little-Endian user selectable byte representation  
5V input tolerant  
Fixed, low first word latency  
FUNCTIONALBLOCKDIAGRAM  
*Available on the PBGA package only.  
D0 -Dn (x36, x18 or x9)  
LD SEN  
WEN  
WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
HF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
ASYW  
*
FWFT/SI  
PFM  
RAM ARRAY  
FSEL0  
FSEL1  
1,024 x 36, 2,048 x 36  
4,096 x 36, 8,192 x 36  
16,384 x 36, 32,768 x 36  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
READ  
CONTROL  
LOGIC  
RM  
ASYR  
BM  
IW  
OW  
OUTPUT REGISTER  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
JTAG CONTROL  
(BOUNDARY SCAN)  
*
TMS  
TDI  
TDO  
4667 drw01  
*
Q0 -Qn (x36, x18 or x9)  
OE  
*
*
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncIIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
OCTOBER2014  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4667/17  

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