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72V3656L10PFI8

更新时间： 2024-11-30 10:59:23
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
39页 381K
描述
TQFP-128, Reel

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中文翻译

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72V3656L10PFI8 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TQFP
包装说明：,针数：128
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.92
JESD-609代码：e0湿度敏感等级：3
峰值回流温度（摄氏度）：225端子面层：Tin/Lead (Sn/Pb)
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

72V3656L10PFI8 数据手册

 浏览型号72V3656L10PFI8的Datasheet PDF文件第2页浏览型号72V3656L10PFI8的Datasheet PDF文件第3页浏览型号72V3656L10PFI8的Datasheet PDF文件第4页浏览型号72V3656L10PFI8的Datasheet PDF文件第5页浏览型号72V3656L10PFI8的Datasheet PDF文件第6页浏览型号72V3656L10PFI8的Datasheet PDF文件第7页 
3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
IDT72V3656  
IDT72V3666  
IDT72V3676  
• Serial or parallel programming of partial flags  
• Big- or Little-Endian format for word and byte bus sizes  
• Loopback mode on Port A  
FEATURES  
• Memory storage capacity:  
IDT72V3656  
IDT72V3666  
IDT72V3676  
–
–
–
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
• Retransmit Capability  
• Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
• Mailbox bypass registers for each FIFO  
• Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
• Auto power down minimizes power dissipation  
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
• Pin and functionally compatible versions of the 5V parts,  
IDT723656/723666/723676  
• Pin compatible to the lower density parts, IDT72V3626/3636/3646  
• Industrial temperature range (–40°C to +85°C) is available  
• Clock frequencies up to 100 MHz (6.5ns access time)  
• Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
• Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
• Programmable Almost-Empty and Almost-Full flags; each has  
five default offsets (8, 16, 64, 256 and 1,024)  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
CLKA  
CSA  
Register  
Port-A  
Control  
Logic  
18  
W/RA  
B0-B17  
ENA  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
MBA  
36  
36  
LOOP  
CLKB  
Port-B  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
RENB  
Control  
CSB  
MBB  
Logic  
Read  
Pointer  
Write  
Pointer  
SIZEB  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AFA  
AEB  
FIFO1  
FIFO2  
Common  
Port  
FS2  
FS0/SD  
FS1/SEN  
A0-A35  
Control  
Logic  
Programmable Flag  
Offset Registers  
Timing  
Mode  
BE  
(B and C)  
13  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
18  
36  
36  
C0-C17  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
Mail 2  
Register  
SIZEC  
4665 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
FEBRUARY 2009  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4665/5  
1234567...39

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72V3656L15PF8 IDT

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72V3656L15PFG IDT

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72V3660 RENESAS

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72V3660L10PFG8 IDT

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72V3660L15PFGI8 IDT

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 		FIFO, 4KX36, 10ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
72V3660L6BBG8 IDT

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 		FIFO, 4KX36, 4ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-
72V3660L7-5BBG8 IDT

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 		FIFO, 4KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-
72V3660L7-5BBGI8 IDT

获取价格

 		FIFO, 4KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-

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