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72V3664 PDF预览

72V3664

更新时间: 2024-09-30 14:58:23
品牌 Logo 应用领域
瑞萨 - RENESAS 先进先出芯片
页数 文件大小 规格书
38页 449K
描述
4K x 36 x 2 SyncBiFIFO, 3.3V

72V3664 数据手册

 浏览型号72V3664的Datasheet PDF文件第2页浏览型号72V3664的Datasheet PDF文件第3页浏览型号72V3664的Datasheet PDF文件第4页浏览型号72V3664的Datasheet PDF文件第5页浏览型号72V3664的Datasheet PDF文件第6页浏览型号72V3664的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
WITH BUS-MATCHING  
4,096 x 36 x 2  
IDT72V3664  
Big- or Little-Endian format for word and byte bus sizes  
Retransmit Capability  
FEATURES  
Memory storage capacity:  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Auto power down minimizes power dissipation  
Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible version of the 5V operating  
IDT723664  
IDT72V3664  
4,096 x 36 x 2  
Clock frequencies up to 100 MHz (6.5ns access time)  
Two independent clocked FIFOs buffering data in opposite  
directions  
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRB flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has five  
default offsets (8, 16, 64, 256 and 1,024 )  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
36  
36  
RAM ARRAY  
4,096 x 36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO1  
FIFO2  
FS2  
FS0/SD  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS1/SEN  
B0-B35  
A0-A35  
13  
Status Flag  
Logic  
EFA/ORA  
FFB/IRB  
AFB  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
36  
36  
RAM ARRAY  
4,096 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
MBF2  
SIZE  
4664 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
JUNE 2016  
COMMERCIAL TEMPERATURE RANGE  
1
©
DSC-4664/7  

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