Datasheet > 72V3653L15PFG

72V3653L15PFG

更新时间： 2024-02-11 15:09:19

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片配套器件
页数	文件大小	规格书
30页	184K
描述
3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING

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中文翻译

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数据手册

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72V3653L15PFG 数据手册

3.3 VOLT CMOS SyncFIFO^TMWITH BUS-MATCHING

2,048 x 36

4,096 x 36

8,192 x 36

IDT72V3653

IDT72V3663

IDT72V3673

• Retransmit Capability

• Reset clears data and configures FIFO, Partial Reset clears data

but retains configuration settings

FEATURES

• Memory storage capacity:

IDT72V3653

IDT72V3663

IDT72V3673

–

2,048 x 36

4,096 x 36

8,192 x 36

• Mailbox bypass registers for each FIFO

• Free-running CLKA and CLKB may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

• Clock frequencies up to 100 MHz (6.5 ns access time)

• Clocked FIFO buffering data from Port A to Port B

• IDT Standard timing (using EF and FF) or First Word Fall

Through Timing (using OR and IR flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has

five default offsets (8, 16, 64, 256 and 1,024)

• Serial or parallel programming of partial flags

• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

• Easily expandable in width and depth

• Auto power down minimizes power dissipation

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

• Pin and functionally compatible versions of the 5V operating

IDT723653/723663/723673

• Pin compatible with the lower density parts, IDT72V3623/

72V3633/72V3643

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Big- or Little-Endian format for word and byte bus sizes

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

Port-A

W/RA

Control

ENA

Logic

MBA

RAM ARRAY

FIFO1

Mail1,

Mail2,

Reset

Logic

2,048 x 36

4,096 x 36

8,192 x 36

RS1

RS2

PRS

RTM

FIFO

Retransmit

Logic

Write

Pointer

Read

Pointer

A0-A35

B0-B35

Status Flag

Logic

EF/OR

FF/IR

FS2

FS0/SD

FS1/SEN

Programmable Flag

Offset Registers

Timing

Mode

FWFT

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

SIZE

Mail 2

4662 drw01

MBF2

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncFIFO™isatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 2016

DSC-4662/5

12 3 4 5 6 7...30

中文翻译

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与72V3653L15PFG相关器件

型号	品牌	获取价格	描述	数据表
72V3653L15PFG8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING
72V3656L10PF	IDT	获取价格	TQFP-128, Tray
72V3656L10PF8	IDT	获取价格	TQFP-128, Reel
72V3656L10PFG	IDT	获取价格	Bi-Directional FIFO, 2KX36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128
72V3656L10PFI	IDT	获取价格	TQFP-128, Tray
72V3656L10PFI8	IDT	获取价格	TQFP-128, Reel
72V3656L15PF	IDT	获取价格	TQFP-128, Tray
72V3656L15PF8	IDT	获取价格	TQFP-128, Reel
72V3656L15PFG	IDT	获取价格	3.3 VOLT CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
72V3660	RENESAS	获取价格	4K x 36 SuperSync II FIFO, 3.3V

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