Datasheet > 72V36104L10PFG

72V36104L10PFG

更新时间： 2024-11-25 06:52:03

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
36页	348K
描述
Bi-Directional FIFO, 64KX36, 6.5ns, Synchronous, CMOS, PQFP128, GREEN, TQFP-128

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中文翻译

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数据手册

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72V36104L10PFG 数据手册

3.3 VOLT CMOS SyncBiFIFO^TMWITH BUS-MATCHING

16,384 x 36 x 2

32,768 x 36 x 2

65,536 x 36 x 2

IDT72V3684

IDT72V3694

IDT72V36104

• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

• Big- or Little-Endian format for word and byte bus sizes

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

FEATURES

• Memory storage capacity:

IDT72V3684

IDT72V3694

IDT72V36104 – 65,536 x 36 x 2

–

16,384 x 36 x 2

32,768 x 36 x 2

• Mailbox bypass registers for each FIFO

• Clock frequencies up to 100 MHz (6.5ns access time)

• Two independent clocked FIFOs buffering data in opposite

directions

• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has five

default offsets (8, 16, 64, 256 and 1,024 )

• Serial or parallel programming of partial flags

• Retransmit Capability

• Free-running CLKA and CLKB may be asynchronous or coincident

(simultaneous reading and writing of data on a single clock edge

is permitted)

• Auto power down minimizes power dissipation

• Available in space saving 128-pin Thin Quad Flatpack (TQFP)

• Pin compatible to the lower density parts, IDT72V3624/72V3634/

72V3644/72V3654/72V3664/72V3674

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

W/RA

ENA

Port-A

Control

Logic

RAM ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

MBA

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

Write

Pointer

Read

Pointer

Status Flag

Logic

FFA/IRA

EFB/ORB

AEB

AFA

FIFO1

FIFO2

FS2

FS0/SD

FS1/SEN

A⁰-A35

Programmable Flag

Offset Registers

Timing

Mode

FWFT

B0-B35

Status Flag

EFA/ORA

FFB/IRB

AFB

Logic

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RT1

RTM

RT2

FIFO1 and

FIFO2

Retransmit

Logic

RAM ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

Mail 2

4677 drw01

MBF2

SIZE

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

FEBRUARY 2009

DSC-4677/8

12 3 4 5 6 7...36

中文翻译

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与72V36104L10PFG相关器件

型号	品牌	获取价格	描述	数据表
72V36104L15PFG	IDT	获取价格	Bi-Directional FIFO, 64KX36, 10ns, Synchronous, CMOS, PQFP128, GREEN, TQFP-128
72V36106L10PF9	IDT	获取价格	TQFP-128, Tray
72V3611	RENESAS	获取价格	64 x 36 SyncFIFO, 3.3V
72V36110	RENESAS	获取价格	128K x 36 SuperSync II FIFO, 3.3V
72V36110L10BBG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PF8	IDT	获取价格	TQFP-128, Reel
72V36110L10PFG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II

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