Datasheet > 72V36106L10PF9

72V36106L10PF9

更新时间： 2024-09-16 08:57:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
39页	389K
描述
TQFP-128, Tray

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中文翻译

获取价格

数据手册

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72V36106L10PF9 数据手册

3.3 VOLT CMOS TRIPLE BUS SyncFIFO^TMWITH BUS-MATCHING

16,384 x 36 x 2

32,768 x 36 x 2

65,536 x 36 x 2

IDT72V3686

IDT72V3696

IDT72V36106

• Serial or parallel programming of partial flags

FEATURES

• Big- or Little-Endian format for word and byte bus sizes

• Loopback mode on Port A

• Retransmit Capability

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

• Mailbox bypass registers for each FIFO

• Free-running CLKA, CLKB and CLKC may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

• Auto power down minimizes power dissipation

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

• Pin compatible to the lower density parts, IDT72V3626/72V3636/

72V3646/72V3656/72V3666/72V3676

• Memory storage capacity:

IDT72V3686 – 16,384 x 36 x 2

IDT72V3696 – 32,768 x 36 x 2

IDT72V36106 – 65,536 x 36 x 2

• Clock frequencies up to 100 MHz (6.5ns access time)

• Two independent FIFOs buffer data between one bidirectional

36-bit port and two unidirectional 18-bit ports (Port C receives

and Port B transmits)

• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on

Ports B and C

• Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRC flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has

five default offsets (8, 16, 64, 256 and 1024)

• Industrial temperature range (–40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

Port-A

Control

Logic

W/RA

ENA

B0-B17

RAM ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

MBA

LOOP

CLKB

RENB

CSB

Port-B

Control

Logic

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

MBB

Read

Pointer

Write

Pointer

SIZEB

Status Flag

Logic

FFA/IRA

EFB/ORB

AFA

AEB

FIFO1

FIFO2

Common

Port

FS2

FS0/SD

Control

Logic

Programmable Flag

Offset Registers

Timing

Mode

FS1/SEN

(B and C)

A0-A35

FWFT

FFC/IRC

AFC

Status Flag

Logic

EFA/ORA

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RT1

RTM

RT2

FIFO1 and

FIFO2

Retransmit

Logic

RAM ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

C0-C17

CLKC

WENC

MBC

Port-C

Control

Logic

Mail 2

SIZEC

4676 drw01

MBF2

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERICAL TEMPERATURE RANGE

NOVEMBER 2003



DSC-4676/4

12 3 4 5 6 7...39

中文翻译

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与72V36106L10PF9相关器件

型号	品牌	获取价格	描述	数据表
72V3611	RENESAS	获取价格	64 x 36 SyncFIFO, 3.3V
72V36110	RENESAS	获取价格	128K x 36 SuperSync II FIFO, 3.3V
72V36110L10BBG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PF8	IDT	获取价格	TQFP-128, Reel
72V36110L10PFG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PFG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PFGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II

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