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72V36110L10PFG PDF预览

72V36110L10PFG

更新时间: 2024-11-07 00:31:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
48页 310K
描述
3.3 VOLT HIGH-DENSITY SUPERSYNC II

72V36110L10PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP128,.63X.87,20针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.48
最长访问时间:6.5 ns其他特性:RETRANSMIT; AUTO POWER DOWN; ASYNCHRONOUS MODE IS ALSO POSSIBLE
最大时钟频率 (fCLK):100 MHz周期时间:10 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e3
长度:20 mm内存密度:4718592 bit
内存集成电路类型:OTHER FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.015 A子类别:FIFOs
最大压摆率:0.04 mA最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mm

72V36110L10PFG 数据手册

 浏览型号72V36110L10PFG的Datasheet PDF文件第2页浏览型号72V36110L10PFG的Datasheet PDF文件第3页浏览型号72V36110L10PFG的Datasheet PDF文件第4页浏览型号72V36110L10PFG的Datasheet PDF文件第5页浏览型号72V36110L10PFG的Datasheet PDF文件第6页浏览型号72V36110L10PFG的Datasheet PDF文件第7页 
3.3 VOLT HIGH-DENSITY SUPERSYNC II™  
36-BIT FIFO  
65,536 x 36  
131,072 x 36  
IDT72V36100  
IDT72V36110  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
JTAG port, provided for Boundary Scan function (PBGA Only)  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic  
Ball Grid Array (PBGA) (with additional features)  
Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/  
72V3670/72V3680/72V3690)family  
FEATURES:  
Choose among the following memory organizations:  
IDT72V36100  
IDT72V36110  
65,536 x 36  
131,072 x 36  
Higher density, 2Meg and 4Meg SuperSync II FIFOs  
Up to 166 MHz Operation of the Clocks  
UserselectableAsynchronousreadand/orwriteports(PBGAOnly)  
User selectable input and output port bus-sizing  
- x36 in to x36 out  
- x36 in to x18 out  
- x36 in to x9 out  
- x18 in to x36 out  
- x9 in to x36 out  
Big-Endian/Little-Endian user selectable byte representation  
5V input tolerant  
Fixed, low first word latency  
Zero latency retransmit  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable settings  
FUNCTIONALBLOCKDIAGRAM  
*Available on the PBGA package only.  
D0 -Dn (x36, x18 or x9)  
LD SEN  
WEN  
WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
FLAG  
LOGIC  
PAE  
HF  
FWFT/SI  
PFM  
FSEL0  
FSEL1  
WRITE CONTROL  
LOGIC  
ASYW  
*
RAM ARRAY  
65,536 x 36  
131,072 x 36  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
RM  
ASYR  
READ  
CONTROL  
LOGIC  
BM  
IW  
OW  
OUTPUT REGISTER  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
TMS  
TDI  
TDO  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
*
6117 drw01  
*
Q0 -Qn (x36, x18 or x9)  
OE  
*
*
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncIIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
DECEMBER 2016  
1
©
2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6117/15  

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