Datasheet > 72V3611

72V3611

更新时间： 2024-11-10 14:57:47

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
20页	248K
描述
64 x 36 SyncFIFO, 3.3V

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中文翻译

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数据手册

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72V3611 数据手册

3.3 VOLT CMOS SyncFIFO^TM

64 x 36

72V3611

• Available in space-saving 120-pin Thin Quad Flatpack (PFG)

Green parts available, see ordering information

FEATURES:

•

• 64 x 36 storage capacity

• Supports clock frequencies up to 67MHz

• Fast access times of 10ns

• Free-running CLKA and CLKB may be asynchronous or

coincident (permits simultaneous reading and writing of

data on a single clock edge)

• Synchronous data buffering from Port A to Port B

• Mailbox bypass register in each direction

• Programmable Almost-Full (AF) and Almost-Empty (AE) flags

• Microprocessor Interface Control Logic

• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA

• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by

CLKB

DESCRIPTION:

TheIDT72V3611isdesignedtorunoffa3.3Vsupplyforexceptionallylow

power consumption. This device is a monolithic, high-speed, low-power,

CMOSSynchronous(clocked)FIFOmemorywhichsupportsclockfrequen-

ciesupto67MHzandhasreadaccesstimesasfastas10ns.The64 x 36dual-

portFIFObuffersdatafromPortAtoPortB.TheFIFOoperatesinIDTStandard

modeandhasflagstoindicateemptyandfullconditions,andtwoprogrammable

flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected

numberofwordsisstoredinmemory. Communicationbetweeneachportcan

takeplacethroughtwo36-bitmailboxregisters. Eachmailboxregisterhasa

flagtosignalwhen newmailhasbeenstored. Parityischeckedpassivelyon

eachportandmaybeignoredifnotdesired. Paritygenerationcanbeselected

• Passive parity checking on each Port

• Parity Generation can be selected for each Port

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

Port-A

Control

Logic

MBA

MBF1

PEFB

Parity

Gen/Check

Mail 1

PGB

RST

Reset

Logic

ODD/

EVEN

RAM

ARRAY

64 x 36

- A35

Read

Pointer

Write

Pointer

B0 - B35

Status Flag

Logic

FIFO

Programmable

Flag Offset

Registers

PGA

Mail 2

Parity

Gen/Check

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

PEFA

MBF2

4657 drw01

COMMERCIAL TEMPERATURE RANGE

Feb.10.20

12 3 4 5 6 7...20

中文翻译

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与72V3611相关器件

型号	品牌	获取价格	描述	数据表
72V36110	RENESAS	获取价格	128K x 36 SuperSync II FIFO, 3.3V
72V36110L10BBG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10BBGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PF8	IDT	获取价格	TQFP-128, Reel
72V36110L10PFG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PFG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PFGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36110L10PFGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II