Datasheet > 72V251L20PFGI

72V251L20PFGI

更新时间： 2024-11-07 00:46:31

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
14页	285K
描述
3.3 VOLT CMOS SyncFIFO

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

72V251L20PFGI 数据手册

3.3 VOLT CMOS SyncFIFO™

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

IDT72V201, IDT72V211

IDT72V221, IDT72V231

IDT72V241, IDT72V251

4,096 x 9 and 8,192 x 9

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin

assignments are identical to those of the IDT72201/72211/72221/72231/

72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand

3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-

bitmemoryarray,respectively.TheseFIFOsareapplicableforawidevariety

ofdatabufferingneedssuchasgraphics,localareanetworksandinterprocessor

communication.

FEATURES:

• 256 x 9-bit organization IDT72V201

• 512 x 9-bit organization IDT72V211

• 1,024 x 9-bit organization IDT72V221

• 2,048 x 9-bit organization IDT72V231

• 4,096 x 9-bit organization IDT72V241

• 8,192 x 9-bit organization IDT72V251

• 10 ns read/write cycle time

These FIFOs have 9-bit input and output ports. The input port is

controlled by a free-running clock (WCLK), and two Write Enable pins

(WEN1, WEN2). Data is written into the Synchronous FIFO on every

rising clock edge when the Write Enable pins are asserted. The output

port is controlled by another clock pin (RCLK) and two Read Enable pins

(REN1, REN2). The Read Clock can be tied to the Write Clock for single

clock operation or the two clocks can run asynchronous of one another

for dual-clock operation. An Output Enable pin (OE) is provided on the

read port for three-state control of the output.

TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).

Twoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF),are

provided for improved system control. The programmable flags default to

Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag

offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting

the Load pin (LD).

• 5V input tolerant

• Read and Write clocks can be independent

• Dual-Ported zero fall-through time architecture

• Empty and Full Flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags can be set to

any depth

• Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

• Output Enable puts output data bus in high-impedance state

• Advanced submicron CMOS technology

• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin

plastic Thin Quad FlatPack (TQFP)

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

These FIFOs are fabricated using high-speed submicron CMOS

technology.

DESCRIPTION:

TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™

FUNCTIONAL BLOCK DIAGRAM

D0 - D8

WCLK

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

PAE

PAF

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

READ POINTER

WRITE POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

4092 drw 01

Q0 - Q8

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

AUGUST 2013

DSC-4092/6

12 3 4 5 6 7...14

中文翻译

下载PDF

与72V251L20PFGI相关器件

型号	品牌	获取价格	描述	数据表
72V251L20PFGI8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V253	RENESAS	获取价格	4K x 18 / 8K x 9 SuperSync II FIFO, 3.3V
72V253L6BC	IDT	获取价格	CABGA-100, Tray
72V253L6BCG8	IDT	获取价格	FIFO, 4KX18, 4ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100
72V253L6PF	IDT	获取价格	TQFP-80, Tray
72V253L6PF8	IDT	获取价格	TQFP-80, Reel
72V253L7-5BC	IDT	获取价格	CABGA-100, Tray
72V253L7-5BCG	IDT	获取价格	FIFO, 4KX18, 5ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100
72V253L7-5BCG8	IDT	获取价格	FIFO, 4KX18, 5ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100
72V253L7-5BCGI	IDT	获取价格	FIFO, 4KX18, 5ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100

与72V251L20PFGI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

72V251L20PFGI

72V251L20PFGI 数据手册

与72V251L20PFGI相关器件

与72V251L20PFGI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

72V251L20PFGI

72V251L20PFGI 数据手册

与72V251L20PFGI相关器件

与72V251L20PFGI相关文章

您还可以找

您在本页遇到什么问题？