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72V243L7-5BCG8 PDF预览

72V243L7-5BCG8

更新时间: 2024-09-13 18:40:03
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
45页 547K
描述
FIFO, 2KX18, 5ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100

72V243L7-5BCG8 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:11 X 11 MM, 1 MM PITCH, GREEN, BGA-100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.72最长访问时间:5 ns
其他特性:IT CAN ALSO BE CONFIGURED AS 4K X 9; RETRANSMIT; ASYNCHRONOUS MODE IS ALSO POSSIBLE周期时间:7.5 ns
JESD-30 代码:S-PBGA-B100长度:11 mm
内存密度:36864 bit内存宽度:18
功能数量:1端子数量:100
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX18
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:1.5 mm
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11 mmBase Number Matches:1

72V243L7-5BCG8 数据手册

 浏览型号72V243L7-5BCG8的Datasheet PDF文件第2页浏览型号72V243L7-5BCG8的Datasheet PDF文件第3页浏览型号72V243L7-5BCG8的Datasheet PDF文件第4页浏览型号72V243L7-5BCG8的Datasheet PDF文件第5页浏览型号72V243L7-5BCG8的Datasheet PDF文件第6页浏览型号72V243L7-5BCG8的Datasheet PDF文件第7页 
3.3VOLTHIGH-DENSITYSUPERSYNCIINARROWBUSFIFO  
512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9  
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9  
8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9  
32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9  
IDT72V223,IDT72V233  
IDT72V243,IDT72V253  
IDT72V263,IDT72V273  
IDT72V283,IDT72V293  
Zero latency retransmit  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
FEATURES:  
Choose among the following memory organizations:  
IDT72V223  
IDT72V233  
IDT72V243  
IDT72V253  
IDT72V263  
IDT72V273  
IDT72V283  
IDT72V293  
512 x 18/1,024 x 9  
Partial Reset clears data, but retains programmable settings  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
JTAG port, provided for Boundary Scan function (BGA Only)  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball  
Grid Array (BGA) (with additional features)  
1,024 x 18/2,048 x 9  
2,048 x 18/4,096 x 9  
4,096 x 18/8,192 x 9  
8,192 x 18/16,384 x 9  
16,384 x 18/32,768 x 9  
32,768 x 18/65,536 x 9  
65,536 x 18/131,072 x 9  
Functionally compatible with the IDT72V255LA/72V265LA and  
IDT72V275/72V285 SuperSync FIFOs  
Up to 166 MHz Operation of the Clocks  
User selectable Asynchronous read and/or write ports (BGA Only)  
User selectable input and output port bus-sizing  
- x9 in to x9 out  
- x9 in to x18 out  
- x18 in to x9 out  
- x18 in to x18 out  
Pin to Pin compatible to the higher density of IDT72V2103/72V2113  
Big-Endian/Little-Endian user selectable byte representation  
5V tolerant inputs  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Fixed, low first word latency  
FUNCTIONAL BLOCK DIAGRAM  
*Available on the  
D0 -Dn (x9 or x18)  
LD SEN  
BGA package only.  
WEN  
WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
ASYW  
RAM ARRAY  
HF  
*
512 x 18 or 1,024 x 9  
FWFT/SI  
PFM  
1,024 x 18 or 2,048 x 9  
2,048 x 18 or 4,096 x 9  
4,096 x 18 or 8,192 x 9  
8,192 x 18 or 16,384 x 9  
16,384 x 18 or 32,768 x 9  
32,768 x 18 or 65,536 x 9  
65,536 x 18 or 131,072 x 9  
FSEL0  
FSEL1  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
READ  
CONTROL  
LOGIC  
RM  
ASYR  
OUTPUT REGISTER  
IW  
OW  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
TMS  
TDI  
TDO  
JTAG CONTROL  
(BOUNDARY SCAN)  
*
4666 drw01  
*
Q0 -Qn (x9 or x18)  
OE  
*
*
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncIIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
JULY 2014  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4666/17  

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