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72V221L10PFG8 PDF预览

72V221L10PFG8

更新时间： 2024-11-24 00:48:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
14页 285K
描述
3.3 VOLT CMOS SyncFIFO

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中文翻译

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72V221L10PFG8 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TQFP
包装说明：LQFP, QFP32,.35SQ,32针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.56
Samacsys Description：TQFP 7MM X 7MM X 1.4MM最长访问时间：6.5 ns
最大时钟频率 (fCLK)：100 MHz周期时间：10 ns
JESD-30 代码：S-PQFP-G32JESD-609代码：e3
长度：7 mm内存密度：9216 bit
内存集成电路类型：OTHER FIFO内存宽度：9
湿度敏感等级：3功能数量：1
端子数量：32字数：1024 words
字数代码：1000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1KX9可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.005 A子类别：FIFOs
最大压摆率：0.02 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mm

72V221L10PFG8 数据手册

 浏览型号72V221L10PFG8的Datasheet PDF文件第2页浏览型号72V221L10PFG8的Datasheet PDF文件第3页浏览型号72V221L10PFG8的Datasheet PDF文件第4页浏览型号72V221L10PFG8的Datasheet PDF文件第5页浏览型号72V221L10PFG8的Datasheet PDF文件第6页浏览型号72V221L10PFG8的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFO™  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
IDT72V201, IDT72V211  
IDT72V221, IDT72V231  
IDT72V241, IDT72V251  
4,096 x 9 and 8,192 x 9  
are very high-speed, low-power First-In, First-Out (FIFO) memories with  
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin  
assignments are identical to those of the IDT72201/72211/72221/72231/  
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand  
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-  
bitmemoryarray,respectively.TheseFIFOsareapplicableforawidevariety  
ofdatabufferingneedssuchasgraphics,localareanetworksandinterprocessor  
communication.  
FEATURES:  
• 256 x 9-bit organization IDT72V201  
• 512 x 9-bit organization IDT72V211  
• 1,024 x 9-bit organization IDT72V221  
• 2,048 x 9-bit organization IDT72V231  
• 4,096 x 9-bit organization IDT72V241  
• 8,192 x 9-bit organization IDT72V251  
• 10 ns read/write cycle time  
These FIFOs have 9-bit input and output ports. The input port is  
controlled by a free-running clock (WCLK), and two Write Enable pins  
(WEN1, WEN2). Data is written into the Synchronous FIFO on every  
rising clock edge when the Write Enable pins are asserted. The output  
port is controlled by another clock pin (RCLK) and two Read Enable pins  
(REN1, REN2). The Read Clock can be tied to the Write Clock for single  
clock operation or the two clocks can run asynchronous of one another  
for dual-clock operation. An Output Enable pin (OE) is provided on the  
read port for three-state control of the output.  
TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).  
Twoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF),are  
provided for improved system control. The programmable flags default to  
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag  
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting  
the Load pin (LD).  
• 5V input tolerant  
• Read and Write clocks can be independent  
• Dual-Ported zero fall-through time architecture  
• Empty and Full Flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags can be set to  
any depth  
• Programmable Almost-Empty and Almost-Full flags default to  
Empty+7, and Full-7, respectively  
• Output Enable puts output data bus in high-impedance state  
• Advanced submicron CMOS technology  
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin  
plastic Thin Quad FlatPack (TQFP)  
• Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
These FIFOs are fabricated using high-speed submicron CMOS  
technology.  
DESCRIPTION:  
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D8  
WCLK  
WEN1  
WEN2  
LD  
INPUT REGISTER  
OFFSET REGISTER  
EF  
FLAG  
LOGIC  
PAE  
PAF  
FF  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
REN1  
REN2  
RS  
OE  
4092 drw 01  
Q0 - Q8  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2013  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4092/6  
1234567...14

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