Datasheet > 72V225

72V225

更新时间： 2024-11-27 14:57:35

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
26页	375K
描述
1K x 18 SyncFIFO, 3.3V

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中文翻译

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数据手册

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72V225 数据手册

3.3 VOLT CMOS SyncFIFO^TM

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

IDT72V205, IDT72V215,

IDT72V225, IDT72V235,

IDT72V245

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

• Industrial temperature range (–40°C to +85°C) is available

FEATURES:

• Green parts available, see ordering information

• 256 x 18-bit organization array (IDT72V205)

• 512 x 18-bit organization array (IDT72V215)

• 1,024 x 18-bit organization array (IDT72V225)

• 2,048 x 18-bit organization array (IDT72V235)

• 4,096 x 18-bit organization array (IDT72V245)

• 10 ns read/write cycle time

DESCRIPTION:

TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-

patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,

designed to run off a 3.3V supply for exceptionally low power consumption.

These devices are very high-speed, low-power First-In, First-Out (FIFO)

memorieswithclockedreadandwritecontrols. TheseFIFOsareapplicable

forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local

AreaNetworks(LANs),andinterprocessorcommunication.

• 5V input tolerant

• IDT Standard or First Word Fall Through timing

• Single or double register-buffered Empty and Full flags

• Easily expandable in depth and width

• Asynchronous or coincident Read and Write Clocks

• Asynchronous or synchronous programmable Almost-Empty

and Almost-Full flags with default settings

• Half-Full flag capability

• Output enable puts output data bus in high-impedance state

• High-performance submicron CMOS technology

• Available in a 64-lead thin quad flatpack (TQFP/STQFP)

TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled

byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread

intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput

portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).

TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation

orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.

AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol

oftheoutput.

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0-D17

WEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

FLAG

WRITE CONTROL

LOGIC

EF/OR

PAE

LOGIC

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

HF/(WXO)

READ POINTER

WRITE POINTER

WXI

READ CONTROL

LOGIC

EXPANSION LOGIC

(HF)/WXO

RXI

RXO

OUTPUT REGISTER

RESET LOGIC

4294 drw 01

REN

RCLK

Q0-Q17

IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

MARCH 2018

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4294/8

12 3 4 5 6 7...26

中文翻译

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与72V225相关器件

型号	品牌	获取价格	描述	数据表
72V225L10PF	IDT	获取价格	TQFP-64, Tray
72V225L10PF8	IDT	获取价格	TQFP-64, Reel
72V225L10PFG	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10PFG8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10PFGI	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10PFGI8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10TFG	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10TFG8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10TFGI	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V225L10TFGI8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO

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