Datasheet > 72V2105L20PF

72V2105L20PF

更新时间： 2024-09-17 10:12:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
26页	241K
描述
TQFP-64, Tray

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中文翻译

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数据手册

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72V2105L20PF 数据手册

3.3 VOLT HIGH DENSITY CMOS

SUPERSYNC FIFO™

131,072 x 18

IDT72V295

IDT72V2105

262,144 x 18

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and writing

simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP)

• High-performance submicron CMOS technology

FEATURES:

• Choose among the following memory organizations:

IDT72V295

IDT72V2105

⎯

131,072 x 18

262,144 x 18

• Pin-compatible with the IDT72V255/72V265 and the IDT72V275/

72V285 SuperSync FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• 5V input tolerant

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

DESCRIPTION:

The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS

First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These

FIFOsoffernumerousimprovementsoverpreviousSuperSyncFIFOs,includ-

ing the following:

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

• The limitationofthe frequencyofone clockinputwithrespecttothe other

has been removed. The Frequency Select pin (FS) has been removed,

• Program partial flags by either serial or parallel means

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

131,072 x 18

262,144 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

4668 drw 01

Q0 -Q17

IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

OCTOBER 2008

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4668/4

12 3 4 5 6 7...26

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