Datasheet > 723626L12PF8

723626L12PF8

更新时间： 2024-02-12 16:21:04

品牌	Logo	应用领域
艾迪悌 - IDT		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
35页	340K
描述
TQFP-128, Reel

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技术参数
数据手册

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723626L12PF8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	TQFP-128	针数：	128
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.55
最长访问时间：	8 ns	其他特性：	MAILBOX
最大时钟频率 (fCLK)：	83 MHz	周期时间：	12 ns
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	内存密度：	9216 bit
内存集成电路类型：	BI-DIRECTIONAL FIFO	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	128	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256X36	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP128,.63X.87,20	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.001 A	子类别：	FIFOs
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

723626L12PF8 数据手册

IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™

WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

each port are independent of one another and can be asynchronous or fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough

coincident. The enables for each port are arranged to provide a simple mode. IR indicates whether or not the FIFO has available memory locations.

bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe

nouscontrol.

CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox

presence of valid data on the outputs.

EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and

registers.Themailboxregisters'widthmatchestheselectedbuswidthofports aprogrammableAlmost-Fullflag(AFAandAFC).AEAandAEBindicatewhen

BandC. Eachmailboxregisterhas a flag(MBF1 andMBF2)tosignalwhen aselectednumberofwordsremainintheFIFOmemory.AFAandAFCindicate

newmailhas beenstored.

whenthe FIFOcontains more thana selectednumberofwords.

TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial

FFA/IRA,FFC/IRC,AFAandAFCaretwo-stagesynchronizedtothePort

Reset. MasterResetinitializesthereadandwritepointerstothefirstlocation Clockthatwritesdataintoitsarray.EFA/ORA,EFB/ORB,AEA,andAEBare

ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram- two-stage synchronized to the Port Clock that reads data from its array.

ming,or oneofthreepossibledefaultflagoffsetsettings,8,16or64. EachFIFO ProgrammableoffsetsforAEA,AEB,AFA,AFCareloadedinparallelusingPort

has its own, independent Master Reset pin, MRS1 and MRS2.

AorinserialviatheSDinput.TheSerialProgrammingModepin(SPM)makes

PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe thisselection.Threedefaultoffsetsettingsarealsoprovided.TheAEAandAEB

memory. UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., thresholdcanbesetat8,16or64locationsfromtheemptyboundaryandthe

programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset AFAandAFCthresholdcanbesetat8,16or64locationsfromthefullboundary.

is useful since it permits flushing of the FIFO memory without changing any AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.

configurationsettings. EachFIFOhasitsown,independentPartialResetpin,

PRS1 and PRS2.

Twoormore FIFOs maybe usedinparalleltocreate widerdata paths.

Suchawidthexpansionrequiresnoadditional,externalcomponents.Further-

These devices have two modes of operation: In the IDT Standard more,twoIDT723626/723636/723646FIFOscanbecombinedwithunidirec-

mode, the first word written to an empty FIFO is deposited into the memory tionalFIFOscapableofFirstWordFallThroughtiming(i.e.theSuperSyncFIFO

array. A read operation is required to access that word (along with all other family)toformadepthexpansion.

words residing in memory). In the First Word Fall Through mode (FWFT),

If, at any time, the FIFO is not actively performing a function, the chip

the first word written to an empty FIFO appears automatically on the willautomaticallypowerdown. Duringthe powerdownstate, supplycurrent

outputs, no read operation required (Nevertheless, accessing subsequent consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol

wordsdoesnecessitateaformalreadrequest). ThestateoftheBE/FWFTpin inputs)willimmediatelytakethedeviceoutofthepowerdownstate.

duringMasterResetdeterminesthemodeinuse.

The IDT723626/723636/723646s are characterized for operation from

Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and 0°Cto70°C. Industrialtemperature range (–40°Cto+85°C)is available by

EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC). specialorder.TheyarefabricatedusingIDT’shighspeed,submicronCMOS

TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates technology.

whether or not the FIFO memory is empty. FF shows whether the memory is

1 234 5 6 7...35

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与723626L12PF8相关器件

型号	品牌	描述	获取价格	数据表
723626L12PFG	IDT	FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128	获取价格
723626L15PFG	IDT	FIFO, 256X36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128	获取价格
723626L15PFG8	IDT	FIFO, 256X36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128	获取价格
723626L20PF	IDT	Bi-Directional FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128	获取价格
723626L20PFI	IDT	Bi-Directional FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128	获取价格
723626L30PF	IDT	Bi-Directional FIFO, 512X36, 15ns, Synchronous, CMOS, PQFP128	获取价格

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