CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2
IDT723626
IDT723636
IDT723646
• Serial or parallel programming of partial flags
FEATURES:
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Memory storage capacity:
IDT723626 – 256 x 36 x 2
IDT723636 – 512 x 36 x 2
IDT723646 – 1,024 x 36 x 2
• Mailbox bypass registers for each FIFO
• Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Clock frequencies up to 83 MHz (8ns access time)
• Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
•
Industrial temperature range (–40°C to +85°C) is available
• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
DESCRIPTION:
The IDT723626/723636/723646 is a monolithic, high-speed, low-
power, CMOS Triple Bus synchronous (clocked) FIFO memory which
supportsclockfrequenciesupto83MHzandhasreadaccesstimesasfastas
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
W/RA
Control
18
B0-B17
ENA
MBA
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
36
Logic
CLKB
RENB
CSB
MBB
SIZEB
FIFO1,
Mail1
Reset
Logic
Port-B
Control
Logic
MRS1
PRS1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
EFB/ORB
FFA/IRA
AEB
AFA
FIFO1
FIFO2
Common
Port
SPM
FS0/SD
Programmable Flag
Offset Registers
Control
Logic
BE
Timing
Mode
FS1/SEN
(B and C)
A0-A35
10
FWFT
Status Flag
Logic
EFA/ORA
FFC/IRC
AFC
AEA
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
36
RAM ARRAY
256 x 36
18
36
36
C0-C17
512 x 36
1,024 x 36
CLKC
WENC
MBC
Port-C
Control
Logic
SIZEC
Mail 2
Register
MBF2
3271 drw01
TheSyncFIFOisatrademarkandtheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
MARCH 2001
1
2001 Integrated Device Technology, Inc.
DSC-3271/2