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723626L12PF8 PDF预览

723626L12PF8

更新时间: 2024-01-20 10:13:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
35页 340K
描述
TQFP-128, Reel

723626L12PF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:TQFP-128针数:128
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.55
最长访问时间:8 ns其他特性:MAILBOX
最大时钟频率 (fCLK):83 MHz周期时间:12 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm内存密度:9216 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:256 words
字数代码:256工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.001 A子类别:FIFOs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

723626L12PF8 数据手册

 浏览型号723626L12PF8的Datasheet PDF文件第4页浏览型号723626L12PF8的Datasheet PDF文件第5页浏览型号723626L12PF8的Datasheet PDF文件第6页浏览型号723626L12PF8的Datasheet PDF文件第8页浏览型号723626L12PF8的Datasheet PDF文件第9页浏览型号723626L12PF8的Datasheet PDF文件第10页 
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION  
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723626/723636/723646 with CLKA,  
CLKBandCLKCsettofS. Alldata inputs anddata outputs change state duringeachclockcycle toconsume the highestsupplycurrent. Data outputs were  
disconnectedtonormalizethegraphtoazerocapacitanceload.Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT723626/723636/  
723646 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.  
CALCULATING POWER DISSIPATION  
WithICC(f) takenfromFigure 1, the maximumpowerdissipation(PT)ofthese FIFOs maybe calculatedby:  
2
PT = VCC x [ICC(f) + (N x ICC x dc)] + Σ(CL x VCC X fo)  
N
where:  
N
ICC  
dc  
CL  
fo  
=
=
=
=
=
number of inputs driven by TTL levels  
increase in power supply current for each input at a TTL HIGH level  
duty cycle of inputs at a TTL HIGH level of 3.4V  
output capacitance load  
switchingfrequencyofanoutput  
300  
250  
f
data = 1/2 fS  
T
A
= 25°C  
C
L
= 0 pF  
VCC = 5.5V  
VCC = 5.0V  
200  
150  
100  
VCC = 4.5V  
50  
0
0
10  
20  
30  
40  
Clock Frequency  
50  
60  
70  
80  
90  
3271 drw02a  
fS  
MHz  
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)  
7

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