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723622L15PQFG PDF预览

723622L15PQFG

更新时间: 2024-11-23 18:17:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
25页 202K
描述
Bi-Directional FIFO, 256X36, 10ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132

723622L15PQFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, SPQFP132,1.1SQ针数:132
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.78
最长访问时间:10 ns其他特性:MAILBOX
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G132JESD-609代码:e3
长度:24.13 mm内存密度:9216 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
功能数量:1端子数量:132
字数:256 words字数代码:256
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256X36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:SPQFP132,1.1SQ
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:4.572 mm最大待机电流:0.001 A
子类别:FIFOs最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.13 mmBase Number Matches:1

723622L15PQFG 数据手册

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CMOS SyncBiFIFOTM  
256 x 36 x 2, 512 x 36 x 2,  
1,024 x 36 x 2  
IDT723622  
IDT723632  
IDT723642  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-  
saving 120-pin Thin Quad Flatpack (TQFP)  
Low-power 0.8-Micron Advanced CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Greenpartsavailable,seeorderinginformation  
FEATURES:  
Memory storage capacity:  
IDT723622  
IDT723632  
IDT723642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Two independent clocked FIFOs buffering data in opposite  
directions  
DESCRIPTION:  
TheIDT723622/723632/723642areamonolithic,high-speed,low-power,  
CMOSBidirectionalSyncFIFO(clocked)memorywhichsupports clockfre-  
quencies up to 83MHz and have read access times as fast as 8ns. Two  
independent256/512/1,024x36dual-portSRAMFIFOsonboardeachchip  
buffer data in opposite directions. Communication between each port may  
bypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailboxregisterhas  
a flag to signal when new mail has been stored.  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
IRA, ORA, AEA, and AFA flags synchronized by CLKA  
IRB, ORB, AEB, and AFB flags synchronized by CLKB  
Supports clock frequencies up to 83MHz  
Fast access times of 8ns  
These devices are a synchronous (clocked) FIFO, meaning each port  
employsasynchronousinterface.Alldatatransfersthroughaportaregated  
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
RAM  
ARRAY  
256 x 36  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
ORB  
AEB  
IRA  
AFA  
FIFO 1  
Programmable Flag  
Offset Registers  
FS  
0
1
B0 - B35  
FS  
A
0
- A35  
10  
FIFO 2  
ORA  
AEA  
Status Flag  
Logic  
IRB  
AFB  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
Port-B  
Control  
Logic  
1,024 x 36  
W/RB  
ENB  
MBB  
Mail 2  
Register  
3022 drw 01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2009  
COMMERCIAL TEMPERATURE RANGE  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3022/5  

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