Datasheet > 723624

723624

更新时间： 2024-11-20 14:57:27

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
35页	244K
描述
256 x 36 x 2 SyncBiFIFO, 5.0V

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中文翻译

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数据手册

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723624 数据手册

CMOS SyncBiFIFO^TMWITH BUS-MATCHING

256 x 36 x 2,

512 x 36 x 2,

1,024 x 36 x 2

IDT723624

IDT723634

IDT723644

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

• Serial or parallel programming of partial flags

• Port B bus sizing of 36-bits (long word), 18-bits (word) and

9-bits (byte)

• Big- or Little-Endian format for word and byte bus sizes

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

• Mailbox bypass registers for each FIFO

• Free-running CLKA and CLKB may be asynchronous or coinci-

dent (simultaneous reading and writing of data on a single clock

edge is permitted)

FEATURES:

• Memory storage capacity:

IDT723624

IDT723634

IDT723644

–

256 x 36 x 2

512 x 36 x 2

1,024 x 36 x 2

• Clock frequencies up to 67 MHz (10 ns access time)

• Two independent clocked FIFOs buffering data in opposite

directions

• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

• Auto power down minimizes power dissipation

• Available in space saving 128-pin Thin Quad Flatpack (TQFP)

• Green parts available, see ordering information

• Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

Port-A

Control

Logic

CSA

W/RA

ENA

RAM ARRAY

256 x 36

MBA

512 x 36

1,024 x 36

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FIFO1

FIFO2

SPM

FS0/SD

FS1/SEN

A⁰-A35

Programmable Flag

Offset Registers

Timing

Mode

FWFT

B0-B35

EFA/ORA

Status Flag

Logic

FFB/IRB

AFB

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RAM ARRAY

256 x 36

512 x 36

CLKB

CSB

W/RB

ENB

MBB

1,024 x 36

Port-B

Control

Logic

Mail 2

SIZE

MBF2

3270 drw01

IDTandtheIDTlogoareregisteredtrademarkofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIALTEMPERATURERANGE

MARCH 2018

DSC-3270/6

12 3 4 5 6 7...35

中文翻译

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与723624相关器件

型号	品牌	获取价格	描述	数据表
723624L12PF	IDT	获取价格	Bi-Directional FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
723624L12PF8	IDT	获取价格	Bi-Directional FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
723624L15PFG	IDT	获取价格	CMOS SyncBiFIFO WITH BUS-MATCHING
723624L15PFG8	IDT	获取价格	CMOS SyncBiFIFO WITH BUS-MATCHING
723624L20PF	IDT	获取价格	Bi-Directional FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128
723624L20PFI	IDT	获取价格	Bi-Directional FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128
723624L30PF	IDT	获取价格	Bi-Directional FIFO, 512X36, 15ns, Synchronous, CMOS, PQFP128
723626L12PF	IDT	获取价格	TQFP-128, Tray
723626L12PF8	IDT	获取价格	TQFP-128, Reel
723626L12PFG	IDT	获取价格	FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128

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