Datasheet > 7202LA50P

7202LA50P

更新时间： 2024-11-19 05:16:51

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
14页	305K
描述
PDIP-28, Tube

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中文翻译

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数据手册
替代型号

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7202LA50P 数据手册

CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

IDT7200L

IDT7201LA

IDT7202LA

•

Industrial temperature range (–40^oC to +85^oC) is available

(plastic packages only)

Green parts available, see ordering information

FEATURES:

• First-In/First-Out dual-port memory

• 256 x 9 organization (IDT7200)

• 512 x 9 organization (IDT7201)

• 1,024 x 9 organization (IDT7202)

• Low power consumption

— Active: 440mW (max.)

DESCRIPTION:

TheIDT7200/7201/7202aredual-portmemoriesthatloadandemptydata

onafirst-in/first-outbasis. ThedevicesuseFullandEmptyflagstopreventdata

overflowandunderflowandexpansionlogictoallowforunlimitedexpansion

capability in both word size and depth.

—Power-down: 28mW (max.)

• Ultra high speed—12ns access time

• Asynchronous and simultaneous read and write

• Fully expandable by both word depth and/or bit width

• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9

• Status Flags: Empty, Half-Full, Full

• Auto-retransmit capability

• High-performance CEMOS™ technology

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing #5962-87531, 5962-89666, 5962-89863

and 5962-89536 are listed on this function

• Dual versions available in the TSSOP package. For more informa-

tion, see IDT7280/7281/7282 data sheet

IDT7280 = 2 x IDT7200

The reads and writes are internally sequential through the use of ring

pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data

istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead

(R) pins.

Thedevicesutilizea9-bitwidedataarraytoallowforcontrolandparitybits

attheuser’soption. Thisfeatureisespeciallyusefulindatacommunications

applicationswhereitisnecessarytouseaparitybitfortransmission/reception

errorchecking. ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset

of the read pointer to its initial position when RT is pulsed LOW to allow for

retransmissionfromthebeginningofdata. AHalf-FullFlagisavailableinthe

singledevicemodeandwidthexpansionmodes.

TheseFIFOsarefabricatedusinghigh-speedCMOStechnology. They

aredesignedforthoseapplicationsrequiringasynchronousandsimultaneous

read/writes in multiprocessing and rate buffer applications. Military grade

productismanufacturedincompliancewithMIL-STD-883,ClassB.

IDT7281 = 2 x IDT7201

IDT7282 = 2 x IDT7202

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(D0-D8)

WRITE

CONTROL

RAM

ARRAY

256 x 9

WRITE

POINTER

READ

POINTER

512 x 9

1,024 x 9

THREE-

STATE

BUFFERS

DATA OUTPUTS

READ

(Q0-Q8)

RESET

LOGIC

CONTROL

FLAG

LOGIC

FL/RT

EXPANSION

2679 drw 01

XO/HF

LOGIC

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.

JUNE 2012

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES

DSC-2679/13

12 3 4 5 6 7...14

中文翻译

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7202LA50P 替代型号

型号	品牌	替代类型	描述	数据表
7202LA12PDG	IDT	类似代替	FIFO, 1KX9, 12ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, GREEN, PLASTIC, DIP-28
IDT7202LA50SO8	IDT	类似代替	FIFO, 1KX9, 50ns, Asynchronous, CMOS, PDSO28, PLASTIC, SOIC-28

与7202LA50P相关器件

型号	品牌	获取价格	描述	数据表
7202LA50PB	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
7202LA50PG	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
7202LA50SO	IDT	获取价格	SOIC-28, Tube
7202LA50SOG	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, PDSO28, GREEN, SOIC-28
7202LA50TC	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, CDIP28
7202LA50TD	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, CDIP28
7202LA50TDG	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, CDIP28
7202LA50TPB	IDT	获取价格	FIFO, 1KX9, 50ns, Asynchronous, CMOS, PDIP28, THIN, PLASTIC, DIP-28
7202LA65DB	IDT	获取价格	FIFO, 1KX9, 65ns, Asynchronous, CMOS, CDIP28
7202LA65P	IDT	获取价格	FIFO, 1KX9, 65ns, Asynchronous, CMOS, PDIP28

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