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71V67803133BQGI PDF预览

71V67803133BQGI

更新时间： 2024-02-03 20:41:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
23页 424K
描述
Cache SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165

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71V67803133BQGI 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA,针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.67
Is Samacsys：N最长访问时间：4.2 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：13 mm
Base Number Matches：1

71V67803133BQGI 数据手册

 浏览型号71V67803133BQGI的Datasheet PDF文件第1页浏览型号71V67803133BQGI的Datasheet PDF文件第3页浏览型号71V67803133BQGI的Datasheet PDF文件第4页浏览型号71V67803133BQGI的Datasheet PDF文件第5页浏览型号71V67803133BQGI的Datasheet PDF文件第6页浏览型号71V67803133BQGI的Datasheet PDF文件第7页 
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with  
3.3V I/O, Pipelined Outputs, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
PinDefinitions(1)  
Symbol  
Pin Function  
I/O  
Active  
Description  
A0-A18  
Address Inputs  
I
N/A  
Synchronous Address inputs. The address register is triggered by a combination of the  
rising edge of CLK and ADSC Low or ADSP Low and CE Low.  
Address Status  
I
I
I
LOW  
LOW  
LOW  
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is  
ADSC  
ADSP  
ADV  
(Cache Controller)  
used to load the address registers with new addresses.  
Address Status  
(Processor)  
Synchronous Address Status from Processor. ADSP is an active LOWinput that is used to  
load the address registers with new addresses. ADSP is gated by CE.  
Burst Address  
Advance  
Synchronous Address Advance. ADV is an active LOW input that is used to advance the  
internal burst counter, controlling burst access after the initial address is loaded. When the  
inputis HIGH the burst counter is not incremented; that is, there is no address advance.  
Byte Write Enable  
I
LOW  
Synchronous byte write enable gates the byte write inputs BW  
1
-BW . If BWE is LOW at the  
4
BWE  
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is  
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.  
Individual Byte  
Write Enables  
I
I
I
LOW  
LOW  
N/A  
Synchronous byte write enables. BW  
1
controls I/O0-7, I/OP1, BW  
2
controls I/O8-15, I/OP2, etc.  
BW  
1
-BW  
4
Any active byte write causes all outputs to be disabled.  
Chip Enable  
Synchronous chip enable. CE is used with CS  
CE also gates ADSP.  
0
and CS1 to enable the IDT71V67603/7803.  
CE  
CLK  
Clock  
This is the clock input. All timing references for the device are made with respect to this  
input.  
CS  
CS  
GW  
0
Chip Select 0  
Chip Select 1  
I
I
I
HIGH  
LOW  
LOW  
Synchronous active HIGH chip select. CS  
0
is used with CE and CS  
1
to enable the chip.  
Synchronous active LOW chip select. CS  
1
is used with CE and CS0 to enable the chip.  
1
Global Write  
Enable  
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW  
on the rising edge of CLK. GW supersedes individual byte write enables.  
I/O  
I/OP1-I/OP4  
0
-I/O31  
Data Input/Output  
I/O  
I
N/A  
Synchronous data input/output (I/O) pins. Both the data input path and data output path are  
registered and triggered by the rising edge of CLK.  
Linear Burst Order  
LOW  
Asynchronous burstorder selection input. When LBO is HIGH, the interleaved burst  
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a  
static input and must not change state while the device is operating.  
LBO  
Output Enable  
I
LOW  
Asynchronous output enable. When OE is LOW the data outputdrivers are enabled on the  
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-  
impedance state.  
OE  
V
DD  
DDQ  
SS  
Power Supply  
Power Supply  
Ground  
N/A  
N/A  
N/A  
N/A  
I
N/A  
N/A  
3.3V core power supply.  
V
3.3V I/O Supply.  
V
N/A  
Ground.  
NC  
ZZ  
No Connect  
Sleep Mode  
N/A  
NC pins are not electrically connected to the device.  
HIGH  
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the  
IDT71V67603/7803 to its lowest power consumption level. Data retention is guaranteed in  
Sleep Mode.  
5310 tbl 02  
NOTE:  
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.  
6.42  
2
1234567...23

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