Datasheet > 71V67803S133BG

71V67803S133BG

更新时间： 2023-01-02 15:25:55

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	424K
描述
PBGA-119, Tray

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71V67803S133BG 数据手册

256K X 36, 512K X 18

IDT71V67603/Z

IDT71V67803/Z

3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

PipelinedOutputs,SingleCycleDeselect

Features

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

the endofthe write cycle.

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high system speed:

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

write enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

◆

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-

pin thinplasticquadflatpack(TQFP), a119ballgridarray(BGA) and a 165

fine pitchballgridarray(fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

PinDescriptionSummary

A0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

5310 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

FEBRUARY 2009

DSC-5310/07

12 3 4 5 6 7...23

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71V67803S133BG8	IDT	PBGA-119, Reel	获取价格
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71V67803S133BGI	IDT	Standard SRAM, 512KX18, 4.2ns, CMOS, PBGA119	获取价格
71V67803S133BQG	ROCHESTER	512KX18 STANDARD SRAM, 4.2ns, PBGA165, 13 X 15 MM, ROHS COMPLIANT, BGA-165	获取价格
71V67803S133PF	IDT	Cache SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
71V67803S133PF8	IDT	Cache SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格

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