Datasheet > 71V67903

71V67903

更新时间： 2024-09-24 14:57:27

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
23页	296K
描述
3.3V 512K x 18 Synchronous 3.3V I/O Flowthrough SRAM

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中文翻译

获取价格

数据手册

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71V67903 数据手册

71V67703

71V67903

256K X 36, 512K X 18

3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

Flow-ThroughOutputs,SingleCycleDeselect

Features

◆

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array (fBGA)

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

256K x 36, 512K x 18 memory configurations

◆

Supports fast access times:

– 7.5ns up to 117MHz clock frequency

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

◆

enable (BWE), and byte writes (BWx)

Green parts available, see ordering information

FunctionalBlockDiagram

LBO

ADV

INTERNAL

Burst

ADDRESS

Sequence

CEN

256K x 36/

CLK

Burst

18/19

Binary

Counter

512K x 18-

BIT

Logic

ADSC

A0*

A1*

MEMORY

ARRAY

CLR

ADSP

CLK EN

A0,A1

A2 - A18

ADDRESS

A0–

17/18

36/18

18/19

BWE

Byte 1

Write Register

Byte 1

Write Driver

Byte 2

Write Register

Byte 2

Write Driver

BW2

Byte 3

Write Register

Byte 3

Write Driver

Byte 4

Write Register

Byte 4

Write Driver

BW4

Enable

DATA INPUT

CLK EN

Powerdown

OUTPUT

BUFFER

36/18

I/O

–I/O31

I/OP1–I/OP4

5309 drw 01

Aug.11.21

12 3 4 5 6 7...23

中文翻译

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