Datasheet > 71V67803

71V67803

更新时间： 2023-12-20 18:45:09

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
23页	297K
描述
3.3V 512K x 18 Synchronous 3.3V I/O PipeLined SRAM

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71V67803 数据手册

71V67603, 71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Symbol

Rating

Commercial

Unit

Grade

Commercial

Industrial

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

VDDQ

(2)

VTERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

3.3V±5%

(3,6)

(4,6)

(5,6)

VTERM

TA⁽⁷⁾

Terminal Voltage with

Respect to GND

-0.5 to VDD

-0.5 to VDD +0.5

-0.5 to VDDQ +0.5

-0 to +70

3.3V±5%

5310 tbl 04

NOTE:

1. TA is the "instant on" case temperature.

Terminal Voltage with

Respect to GND

RecommendedDCOperating

Conditions

Terminal Voltage with

Respect to GND

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min. Typ.

3.135 3.3

Max.

3.465

Unit

^oC

Operating Temperature

DDQ

Temperature

Under Bias

-55 to +125

TBIAS

TSTG

2.0

Storage

-55 to +125

____

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

DD +0.3

Temperature

____

2.0

DDQ +0.3

0.8

Power Dissipation

DC Output Current

2.0

-0.3⁽¹⁾

IOUT

5310 tbl 05

5310 tbl 03

NOTES:

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

165fBGACapacitance

100PinTQFPCapacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

CIN

CI/O

5310 tbl 07

5310 tbl 07b

119BGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

CIN

CI/O

5310 tbl 07a

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.442

Sep.13.21

1 2 345 6 7...23

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71V67803133BQG	IDT	Cache SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165	获取价格
71V67803133BQGI	IDT	Cache SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165	获取价格
71V67803150BGG	IDT	Cache SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, PLASTIC, MS-028AA,	获取价格
71V67803150BGGI	IDT	Cache SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, PLASTIC, MS-028AA,	获取价格
71V67803150BQGI	IDT	Cache SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165	获取价格
71V67803150PFG	IDT	Cache SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, ROHS CO	获取价格

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