Datasheet > 71V67803

71V67803

更新时间： 2023-12-20 18:45:09

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
23页	297K
描述
3.3V 512K x 18 Synchronous 3.3V I/O PipeLined SRAM

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数据手册

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71V67803 数据手册

71V67603, 71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Description

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

and the LBO input pin.

The IDT71V67603/7803 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

the end of the write cycle.

TheIDT71V67603/7803 SRAMsutilizea high-performanceCMOSpro-

cessandarepackagedinaJEDECstandard14mmx20mm100-pinthinplastic

quadflatpack(TQFP), a119ballgridarray(BGA) and a 165 fine pitch ball

grid array (fBGA).

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

PinDescriptionSummary

0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

N/A

5310 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67803.

6.422

Sep.13.21

123 4 5 6 7...23

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71V67803150PFG	IDT	Cache SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, ROHS CO	获取价格