11
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination ofthe rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
ADSC
ADSP
ADV
address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
1
-BW . If BWE is LOW at the rising edge of CLK
4
BWE
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
BW
1
-BW
4
write causes all outputs to be disabled.
Chip Enable
Synchronous chip enable. CE is used with CS
ADSP.
0
and CS to enable the IDT71V35761/781. CE also gates
1
CE
CLK
Clock
I
I
I
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS
CS
GW
0
Chip Select 0
Chip Select 1
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
0
is used with CE and CS
1
to enable the chip.
1
is used with CE and CS0 to enable the chip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
OE
TMS
TDI
Test ModeSelect
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test DataOutput
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
HIGH
TRST
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/35781
to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal
pull down.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
V
V
NC
No Connect
NC pins are not electrically connected to the device.
5301tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
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